at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 222

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

21.11.3
Figure 21-28. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)
222
internally synchronized
NWAIT signal
NBS0, NBS1,
NBS2, NBS3,
A0,A1
AT91SAM9263 Preliminary
Ready Mode
A
D[31:0]
NWAIT
[25:2]
NWE
MCK
NCS
6
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins
the access by down counting the setup and pulse counters of the read/write controlling signal. In
the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in
deassertion, the access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the
pulse of the controlling read/write signal, it has no impact on the access length as shown in
ure
21-29.
4
5
4
3
3
2
1
2
Write cycle
EXNW_MODE = 11 (Ready mode)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
0
1
Wait STATE
0
1
Figure 21-28
0
1
0
and
Figure
6249D–ATARM–20-Dec-07
21-29. After
Fig-