at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 18

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

7.7
18
DMA Controller
AT91SAM9263 Preliminary
• Acts as one Matrix Master
• Embeds 2 unidirectional channels with programmable priority
• Address Generation
• Channel Buffering
• Channel Control
– USART1 Transmit Channel
– USART0 Transmit Channel
– AC97 Transmit Channel
– SPI1 Transmit Channel
– SPI0 Transmit Channel
– SSC1 Transmit Channel
– SSC0 Transmit Channel
– DBGU Receive Channel
– USART2 Receive Channel
– USART1 Receive Channel
– USART0 Receive Channel
– AC97 Receive Channel
– SPI1 Receive Channel
– SPI0 Receive Channel
– SSC1 Receive Channel
– SSC0 Receive Channel
– MCI1 Transmit/Receive Channel
– MCI0 Transmit/Receive Channel
– Source/destination address programming
– Address increment, decrement or no change
– DMA chaining support for multiple non-contiguous data blocks through use of linked
– Scatter support for placing fields into a system memory area from a contiguous
– Gather support for extracting fields from a system memory area into a contiguous
– User enabled auto-reloading of source, destination and control registers from initially
– Auto-loading of source, destination and control registers from system memory at end
– Unaligned system address to data transfer width supported in hardware
– Two 8-word FIFOs
– Automatic packing/unpacking of data to fit FIFO width
– Programmable multiple transaction size for each channel
– Support for cleanly disabling a channel without data loss
lists
transfer. Writing a stream of data into non-contiguous fields in system memory.
transfer
programmed values at the end of a block transfer
of block transfer in block chaining mode
6249D–ATARM–20-Dec-07