at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 109

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

14.3.3
Figure 14-3. BMS Sampling
14.3.4
14.3.4.1
6249D–ATARM–20-Dec-07
proc_nreset
Core Supply
BMS Signal
POR output
BMS Sampling
Reset States
SLCK
General Reset
As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system
power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.
The product matrix manages a boot memory that depends on the level on the BMS pin at reset.
The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising
edge.
The Reset State Manager handles the different reset sources and generates the internal reset
signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The
update of the field RSTTYP is performed when the processor reset is released.
A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR
cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The pur-
pose of this counter is to make sure the Slow Clock oscillator is stable before starting up the
device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup
time.
After this time, the processor clock is released at Slow Clock and all the other signals remain
valid for Y cycles for proper processor and logic reset. Then, all the reset signals are released
and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the
NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0.
When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immedi-
ately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown.
VDDBU only activates the backup_nreset signal.
The backup_nreset must be released so that any other reset can be generated by VDDCORE
(Main Supply POR output).
Figure 14-4
shows how the General Reset affects the reset signals.
XXX
BMS sampling delay
= 3 cycles
H or L
AT91SAM9263 Preliminary
109