at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 271

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

24. DMA Controller (DMAC)
24.1
24.2
Figure 24-1. DMA Controller (DMAC) Block Diagram
24.3
24.3.1
6249D–ATARM–20-Dec-07
Description
Block Diagram
Functional Description
Basic Definitions
DMARQ0..3
AHB Master
AHB Slave
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more AMBA buses. One channel is
required for each source/destination pair. In the most basic configuration, the DMAC has one
master interface and one channel. The master interface reads the data from a source and writes
it to a destination. Two AMBA transfers are required for each DMA data transfer. This is also
known as a dual-access transfer.
The DMAC is programmed via the AHB slave interface.
Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then
stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form
a channel.
Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previ-
ously read from the source peripheral).
Memory: Source or destination that is always “ready” for a DMA transfer and does not require a
handshaking interface to interact with the DMAC. A peripheral should be assigned as memory
AHB Master
Handshaking
AHB Slave
Interface
Interface
Hardware
Interface
DMA Controller
SRC
FSM
Channel 0
CFG
FIFO
Channel 1
DST
FSM
AT91SAM9263 Preliminary
Generator
Interrupt
irq_dma
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