at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1045

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

49.3.11.3
49.3.11.4
49.3.11.5
49.3.11.6
49.3.12
49.3.12.1
6249D–ATARM–20-Dec-07
Serial Synchronous Controller (SSC)
LASTXFER (Last Transfer) Behavior
Baudrate Set to 1
Software Reset
Chip Select and Fixed Mode
Transmitter Limitations in Slave Mode
None. Do not use the combination CSAAT=1 and SCBR =1.
In FIXED Mode with CSAAT bit set and in PDC Mode, the Chip Select can rise depending on the
data written in the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes a
"1" in bit 24 (LASTXFER bit) of the SPI_TDR, the Chip Select rises as soon as the TXEMPTY
flag is set.
Problem Fix/Workaround
Use the CS in PIO mode when PDC Mode is required and CS has to be maintained between
transfers.
When Baudrate is set to 1 (i.e. when serial clock frequency equals the system clock frequency),
and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case
9,11,13 or 15), an additional pulse is generated on output SPCK. No such pulse occurs if BITS
field equals 8,10,12,14 or 16 and Baudrate = 1.
Problem Fix/Workaround
None.
If the Software reset command is performed during the same clock cycle as an event for
TXRDY, there is no reset.
Problem Fix/Workaround
Perform another a software reset.
In fixed Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip
Select 0, the output spi_size sampled by the PDC depends on the field BITS of SPI_CSR0 reg-
ister, whatever the selected Chip select may be. For example, if CSR0 is configured for a 10-bit
transfer, whereas the CSR1 is configured for an 8-bit transfer, when a transfer is performed in
Fixed mode through the PDC on Chip Select 1, the transfer is considered to be a half-word
transfer.
Problem Fix/Workaround
If a PDC transfer has to be performed in 8 bits on a Chip select y (y different from 0), the field
BITS of the CSR0 must be configured in 8 bits in the same way as the field BITS of the CSRy
Register.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when start of edge (rising or falling) of synchro with a Start Delay equal to zero.
Problem Fix/Workaround
None.
AT91SAM9263 Preliminary
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