at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 115

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

14.3.6
Figure 14-9.
14.4
Table 14-1.
Note:
6249D–ATARM–20-Dec-07
Offset
0x00
0x04
0x08
Reset Controller (RSTC) User Interface
1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.
if (URSTEN = 0) and
Peripheral Access
Reset Controller Status Register
(URSTIEN = 1)
Reset Controller (RSTC) Register Mapping
Reset Controller Status and Interrupt
Register
Control Register
Status Register
Mode Register
URSTS
NRSTL
rstc_irq
NRST
MCK
The Reset Controller status register (RSTC_SR) provides several status fields:
resynchronization
• When in Watchdog Reset:
• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no
• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on
• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR
further software reset should be performed until the end of the current one. This bit is
automatically cleared at the end of the current software reset.
each MCK rising edge.
register. This transition is also detected on the Master Clock (MCK) rising edge (see
14-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the
URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the
RSTC_SR status register resets the URSTS bit and clears the interrupt.
2 cycle
– The processor reset is active and so a Software Reset cannot be programmed.
– A User Reset cannot be entered.
Name
RSTC_CR
RSTC_SR
RSTC_MR
resynchronization
AT91SAM9263 Preliminary
Read/Write
2 cycle
Write-only
Read-only
Access
0x0000_0001
Reset Value
RSTC_SR
read
-
-
Back-up Reset
0x0000_0000
0x0000_0000
Value
Figure
115