at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 251

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

22.6.1
Register Name:
Access Type:
Reset Value:
• MODE: SDRAMC Command Mode
This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
6249D–ATARM–20-Dec-07
0
0
0
0
1
1
1
31
23
15
–
–
–
7
–
MODE
SDRAMC Mode Register
0
0
1
1
0
0
1
0
1
0
1
0
1
0
30
22
14
SDRAMC_MR
Read/Write
0x00000000
–
–
–
6
–
Description
Normal mode. Any access to the SDRAM is decoded normally.
The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the
cycle.
The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed
regardless of the cycle.
The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. The address offset with respect to the SDRAM device base address is used to
program the Mode Register. For instance, when this mode is activated, an access to the “SDRAM_Base +
offset” address generates a “Load Mode Register” command with the value “offset” written to the SDRAM
device Mode Register.
The SDRAM Controller issues an “Auto-Refresh” Command when the SDRAM device is accessed
regardless of the cycle. Previously, an “All Banks Precharge” command must be issued.
The SDRAM Controller issues an extended load mode register command when the SDRAM device is
accessed regardless of the cycle. The address offset with respect to the SDRAM device base address is
used to program the Mode Register. For instance, when this mode is activated, an access to the
“SDRAM_Base + offset” address generates an “Extended Load Mode Register” command with the value
“offset” written to the SDRAM device Mode Register.
Deep power-down mode. Enters deep power-down mode.
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
AT91SAM9263 Preliminary
26
18
10
–
–
–
2
MODE
25
17
–
–
9
–
1
24
16
–
–
8
–
0
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