at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1036

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

49.2.16
49.2.16.1
49.2.16.2
49.2.16.3
49.2.16.4
49.2.17
49.2.17.1
1036
AT91SAM9263 Preliminary
Two-wire Interface (TWI)
UDP
Clock Divider
Disabling Does not Operate Correctly
Software Reset
STOP not Generated
Bad Data in the First IN Data Stage
The value of CLDIV x 2
must be less than or equal to 8191·
Problem Fix/Workaround
None.
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with
the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register
(TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts
must be disabled before disabling the TWI.
When a software reset is performed during a frame and when TWCK is low, it is impossible to
initiate a new transfer in READ or WRITE mode.
Problem Fix/Workaround
None.
If the sequence described as follows occurs:
The STOP is not generated.
The line shows: DADR BYTE 1, ..., BYTE n, NO STOP generated, BYTE 1, ..., BYTE n.
Problem Fix/Workaround
Insert a delay of one TWI clock period before step 4.
All or part of the data of the first IN data Stage are not transmitted. It may then be a Zero Length
Packet. The CRC is correct. Thus the HOST may only see that the size of the received data
does not match the requested length. But even if performed again, the control transfer probably
fails.
Problem Fix/Workaround
Control transfers are mainly used at device configuration. After clearing RXSETUP, the software
needs to compute the setup transaction request before writing data into the FIFO if needed. This
1. WRITE 1 or more bytes at a given address.
2. Send a STOP.
3. Wait for TXCOMP flag.
4. READ (or WRITE) 1 or more bytes at the same address.
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
6249D–ATARM–20-Dec-07
CKDIV