at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 276

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

24.3.3.3
24.3.3.4
24.3.3.5
6249D–ATARM–20-Dec-07
Single Transactions
External DMA Request Definition
Hardware Handshaking
asserted in order to initiate a burst transaction. Upon completion of the burst transaction, the
h a r d w a r e c l e a r s t h e D M A C _ S g l R e q S r c R e g [ x ] / D M A C _ S g l R e q D s t R e g [ x ] a n d
DMAC_ReqSrcReg[x]/DMAC_ReqDstReg[x] registers.
Writing a 1 to the DMAC_SglReqSrcReg/DMAC_SglReqDstReg initiates a single transaction.
U p o n
DMAC_SglReqSrcReg/DMAC_SglReqDstReg and DMAC_ReqSrcReg/DMAC_ReqDstReg bits
are cleared by hardware. Therefore, writing a 1 to the DMAC_ReqSrcReg/DMAC_ReqDstReg is
ignored while a single transaction has been initiated, and the requested burst transaction is not
serviced.
Again, writing a 1 to the DMAC_ReqSrcReg/DMAC_ReqDstReg register is always a burst trans-
action request. However, in order for a burst transaction request to start, the corresponding
channel bit in the DMAC_SglReqSrcReg/DMAC_SglReqDstReg must be asserted. Therefore, to
e n s u r e t h a t a b u r s t t r a n s a c t i o n i s s e r v i c e d , y o u m u s t w r i t e a 1 t o t h e
D M A C _ R e q S r c R e g / D M A C _ R e q D s t R e g
DMAC_SglReqSrcReg/DMAC_SglReqDstReg register.
Software can poll the relevant channel bit in the DMAC_SglReqSrcReg/ DMAC_SglReqDstReg
and DMAC_ReqSrcReg/DMAC_ReqDstReg registers. When both are 0, then either the
requested burst or single transaction has completed. Alternatively, the IntSrcTran or IntDstTran
interrupts can be enabled and unmasked in order to generate an interrupt when the requested
source or destination transaction has completed.
Note:
There are 5 hardware handshaking interfaces connected to four external DMA requests (see
Table 24-1 on page
Table 24-1.
When an external slave peripheral requires the DMAC to perform DMA transactions, it communi-
cates its request by asserting the external nDMAREQx signal. This signal is resynchronized to
ensure a proper functionality (see
The external nDMAREQx is asserted when the source threshold level is reached. After resyn-
chronization, the rising edge of dma_req starts the transfer. dma_req is de-asserted when
dma_ack is asserted.
The external nDMAREQx signal must be de-asserted after the last transfer and re-asserted
again before a new transaction starts.
Request
DMAREQ0
DMAREQ1
DMAREQ2
DMAREQ3
The transaction-complete interrupts are triggered when both single and burst transactions are
complete. The same transaction-complete interrupt is used for both single and burst transactions.
c o m p l e t i o n
Hardware Handshaking Connection
276).
Definition
External DMA Request 0
External DMA Request 1
External DMA Request 2
External DMA Request 3
o f
Figure 24-4 on page
t h e
AT91SAM9263 Preliminary
s i n g l e
b e f o r e
277).
t r a n s a c t i o n ,
w r i t i n g
Hardware Handshaking
a
Interface
1
b o t h
1
2
3
4
t o
276
t h e
t h e