ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet
ISP1561BMUM
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1561 Hi-Speed Universal Serial Bus PCI Host Controller Rev. 02 — 5 March 2007 1. General description The ISP1561 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal Serial Bus (USB) Host Controller. It integrates two Original USB Open Host Controller ...
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NXP Semiconductors 2. Features I Complies with I Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) I Two Original USB OHCI cores are compliant with Interface Specification for USB” I One Hi-Speed USB EHCI ...
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NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name ISP1561BM LQFP128 ISP1561_2 Product data sheet Description plastic low profile quad flat package; 128 leads; body 14 Rev. 02 — 5 March 2007 ISP1561 HS USB PCI ...
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PCI-bus PME# 4 CLK 19 AD[31:0] 23, 24, 26, 27, 28, 30, 31, 32, 36, 38, 39, 40, 42, 43, 44, 46, 32 62, 63, 64, 66, 67, 68, 70, 71, C/BE#[3:0] 74, 75, 77, 78, 79, 81, 82, 84 ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration 6.2 Pin description Table 2. [1] Symbol SEL48M SCL SDA PME# V AUX DGND IRQ1 IRQ12 SEL2PORTS V DD ISP1561_2 Product data sheet 1 ISP1561BM 32 Pin description Pin ...
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NXP Semiconductors Table 2. Symbol A20OUT KBIRQ1 MUIRQ12 DGND SMI# INTA RST# CLK GNT# DGND REQ# AD[31] AD[30 AD[29] AD[28] AD[27] DGND AD[26] AD[25] AD[24 C/BE#[3] IDSEL AD[23] DGND AD[22] AD[21] AD[20] ISP1561_2 Product ...
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NXP Semiconductors Table 2. Symbol V DD AD[19] AD[18] AD[17] DGND AD[16] C/BE#[2] FRAME IRDY# TRDY# DEVSEL# DGND STOP# CLKRUN# PERR SERR# PAR C/BE#[1] DGND AD[15] AD[14] AD[13 AD[12] AD[11] AD[10] DGND AD[9] AD[8] ...
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NXP Semiconductors Table 2. Symbol V DD AD[7] AD[6] DGND AD[5] AD[4] AD[ AD[2] AD[1] DGND AD[0] V AUX DGND XTAL1 XTAL2 OC1 PWE1 GL1 AMB1 AV AUX GND_RREF GRN1 OC2 PWE2 ISP1561_2 Product data sheet Pin description ...
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NXP Semiconductors Table 2. Symbol GL2 AMB2 GRN2 AV AUX_PLL DM1 DP1 AGND OC3 PWE3 RREF AV AUX DM2 DP2 AGND GL3 AMB3 GRN3 AV AUX DM3 DP3 AGND OC4 ISP1561_2 Product data sheet Pin description …continued [1] Pin Type ...
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NXP Semiconductors Table 2. Symbol PWE4 AV AUX DM4 DP4 AGND GL4 AMB4 GRN4 DGND [1] Symbol names ending with a ‘#’ (for example, NAME#) represent active LOW signals for PCI pins. Symbol names with an overscore (for example, NAME) ...
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NXP Semiconductors 7. Functional description 7.1 OHCI Host Controller An OHCI Host Controller transfers data to devices at the Original USB defined bit rate of 12 Mbit/s or 1.5 Mbit/s. 7.2 EHCI Host Controller The EHCI Host Controller transfers data ...
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NXP Semiconductors 7.6 Power management The ISP1561 provides an advanced power management capabilities interface that is compliant with controlled and managed by the interaction between drivers and PCI registers. For a detailed description on power management, see 7.7 Legacy support ...
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NXP Semiconductors 8.1.2 PCI initiator and target A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI transactions as a slave. In the ISP1561, the two open Host Controllers and the enhanced Host Controller ...
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NXP Semiconductors Table 3. PCI configuration space registers of OHCI1, OHCI2 and EHCI Address Bits Bits (Hex) 3C MAX_LAT MIN_GNT [7:0] 40 Reserved Enhanced Host Controller-specific PCI registers 60 PORTWAKECAP[15:0] Power management registers DC ...
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NXP Semiconductors 8.2.1.3 Command register (address: 04h) This is a 2-byte register that provides coarse control over the ability of a device to generate and respond to PCI cycles. The bit allocation of the Command register is given in Table ...
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NXP Semiconductors Table 7. Bit 8.2.1.4 Status register (address: 06h) The Status register is a 2-byte read-only register used to record status information on PCI bus-related events (bit allocation: see Table 8. Status register: ...
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NXP Semiconductors Table 9. Bit ISP1561_2 Product data sheet Status register: bit description Symbol Description DPE Detected Parity Error: This bit must be set ...
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NXP Semiconductors 8.2.1.5 Revision ID register (address: 08h) This 1-byte read-only register indicates a device-specific revision identifier. The value is chosen by the vendor. This field is a vendor-defined extension of the device ID. The Revision ID register bit description ...
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NXP Semiconductors 8.2.1.7 CacheLine Size register (address: 0Ch) The CacheLine Size register is a read/write single-byte register that specifies the system cacheline size in units of DWORDs. This register must be implemented by master devices that can generate the Memory ...
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NXP Semiconductors 8.2.1.10 BIST register (address: 0Fh) This register is used for control and status of Built In Self Test (BIST). Devices that do not support BIST must always return logic 0, that is, treat reserved register. ...
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NXP Semiconductors 8.2.1.14 Subsystem ID register (address: 2Eh) Subsystem ID values are vendor-specific. The bit description of the Subsystem ID register is given in Table 19. Subsystem ID register: bit description Bit Symbol Access SID[15:0] R [1] ...
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NXP Semiconductors 8.2.1.18 Interrupt Pin register (address: 3Dh) This 1-byte register is use to specify which interrupt pin the device or device function uses. The bit description is given in Devices or functions that do not use an interrupt pin ...
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NXP Semiconductors 8.2.2 Enhanced Host Controller-specific PCI registers In addition to the PCI configuration header registers, EHCI needs some additional PCI configuration space registers to indicate the serial bus release number, downstream port wake-up event capability, and adjust the USB ...
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NXP Semiconductors Table 29. FLADJ value : 31(1Fh) 32 (20h (3Eh) 63 (3Fh) 8.2.2.3 PORTWAKECAP register (address: 62h) The PORTWAKECAP register is a 2-byte register, and the bit description is given in Table 30. This register is used ...
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NXP Semiconductors 8.2.3.2 NEXT_ITEM_PTR register (address: value read from address 34h + 1h) The Next Item Pointer (NEXT_ITEM_PTR) register (see of the next item in the function’s capability list. The value given is an offset into the function’s PCI configuration ...
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NXP Semiconductors Table 35. Bit The logic level of the AMB4 pin at power-on determines the default value of PMC registers. If this pin is connected to V the case of ...
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NXP Semiconductors Table 36. PMCSR register: bit allocation Bit 15 Symbol PMES [1] Reset X Access R/W Bit 7 Symbol Reset 0 Access - [1] Sticky bit, if the function supports PME# from D3 function does not support PME# from ...
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NXP Semiconductors Table 37. Bit 8.2.3.5 PMCSR_BSE register (address: value read from address 34h + 6h) The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI bridge-specific functionality and is required for all PCI-to-PCI bridges. The bit ...
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NXP Semiconductors Table 40. Originating device’s bridge PM state hot D3 cold 8.2.3.6 Data register (address: value read from address 34h + 7h) The Data register is an optional, 1-byte register that provides a mechanism for ...
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NXP Semiconductors C-bus interface A simple I product ID and some other configuration bits from an external EEPROM. 2 The I C-bus interface is for bidirectional communication between ICs using two serial bus wires: SDA (data) and ...
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NXP Semiconductors 9.3 Information loading from EEPROM Figure 4 default values of Device ID (DID), Vendor ID (VID), subsystem VID and subsystem DID assigned to NXP Semiconductors by PCI-SIG will be loaded. See value. For instructions on programming the EEPROM, ...
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NXP Semiconductors 10.2 USB bus states Reset state — When the USB bus is in the reset state, the USB system is stopped. Operational state — When the USB bus is in the active state, the USB system is operating ...
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Table 42. USB Host Controller registers Address OHCI register (Hex) Func0 OHCI1 (2 ports) 00 HcRevision 0000 0110 04 HcControl 0000 0000 08 HcCommandStatus 0000 0000 0C HcInterruptStatus 0000 0000 10 HcInterruptEnable 0000 0000 14 HcInterruptDisable 0000 0000 18 HcHCCA ...
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Table 42. USB Host Controller registers …continued Address OHCI register (Hex) Func0 OHCI1 (2 ports) 104 HceInput 0000 0000 108 HceOutput 0000 0000 10C HceStatus 0000 0000 [1] Reset values that are highlighted (for example, 0) are the ISP1561 implementation ...
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NXP Semiconductors For the OHCI Host Controller, these registers are divided into two types: one set of operational registers for the USB operation and one set of legacy support registers for the legacy keyboard and mouse operation. For the enhanced ...
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NXP Semiconductors Table 44. Bit 11.1.2 HcControl register (address: content of the base address register + 04h) The HcControl register defines the operating modes for the Host Controller. All the fields in this ...
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NXP Semiconductors Table 46. Bit ISP1561_2 Product data sheet HcControl register: bit description Symbol Description - reserved RWE Remote Wake-up Enable: This bit is used by the HCD to enable ...
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NXP Semiconductors Table 46. Bit 11.1.3 HcCommandStatus register (address: content of the base address register + 08h) The HcCommandStatus register is used by the Host Controller to receive commands issued by the HCD. It ...
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NXP Semiconductors Table 47. HcCommandStatus register: bit allocation Bit 31 Symbol Reset 0 Access - Bit 23 Symbol Reset 0 Access - Bit 15 Symbol Reset 0 Access - Bit 7 Symbol Reset 0 Access - Table 48. Bit 31 ...
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NXP Semiconductors Table 48. Bit 1 0 11.1.4 HcInterruptStatus register (address: content of the base address register + 0Ch) This is a 4-byte register that provides the status of the events that cause hardware interrupts. The bit allocation of the ...
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NXP Semiconductors Bit 7 Symbol reserved RHSC Reset 0 Access - R/W Table 50. Bit 11.1.5 HcInterruptEnable register (address: content of the base address register + 10h) Each ...
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NXP Semiconductors Then, a hardware interrupt is requested on the host bus. Writing logic bit in this register sets the corresponding bit, whereas writing logic bit in this register leaves the corresponding bit unchanged. ...
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NXP Semiconductors Table 52. Bit 11.1.6 HcInterruptDisable register (address: content of the base address register + 14h) Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable ...
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NXP Semiconductors Table 54. Bit 11.1.7 HcHCCA register (address: content of the base address register + 18h) The HcHCCA register contains the physical address of Host Controller Communication ...
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NXP Semiconductors Table 55. HcHCCA register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access - Table ...
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NXP Semiconductors Bit 7 Symbol Reset 0 Access R Table 58. Bit 11.1.9 HcControlHeadED register (address: content of the base address register + 20h) The HcControlHeadED register contains the physical address of the first ...
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NXP Semiconductors 11.1.10 HcControlCurrentED register (address: content of the base address register + 24h) The HcControlCurrentED register contains the physical address of the current ED of the control list. The bit allocation is given in Table 61. HcControlCurrentED register: bit ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W Table 64. Bit 11.1.12 HcBulkCurrentED register (address: content ...
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NXP Semiconductors Table 66. Bit 11.1.13 HcDoneHead register (address: content of the base address register + 30h) The HcDoneHead register contains the physical address of the last completed TD that was added to the ...
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NXP Semiconductors 11.1.14 HcFmInterval register (address: content of the base address register + 34h) The HcFmInterval register contains a 14-bit value that indicates the bit time interval in a frame, that is, between two consecutive SOFs, and a 15-bit value ...
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NXP Semiconductors 11.1.15 HcFmRemaining register (address: content of the base address register + 38h) The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current frame. Table 71. HcFmRemaining register: bit allocation Bit 31 Symbol ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access - Bit 15 Symbol reserved Reset 0 Access - Bit 7 Symbol Reset 0 Access R/W R/W Table 74. Bit 11.1.17 HcPeriodicStart register (address: content of ...
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NXP Semiconductors Bit 7 Symbol Reset 0 Access R/W R/W Table 76. Bit 11.1.18 HcLSThreshold register (address: content of the base address register + 44h) This register contains an 11-bit value used by the ...
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NXP Semiconductors Table 78. Bit 11.1.19 HcRhDescriptorA register (address: content of the base address register + 48h) The HcRhDescriptorA register is the first of two registers describing the characteristics of the root hub. Reset ...
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NXP Semiconductors Table 80. Bit 11.1.20 HcRhDescriptorB register (address: content of the base address register + 4Ch) The HcRhDescriptorB register is the second of two registers ...
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NXP Semiconductors Table 81. HcRhDescriptorB register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W ...
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NXP Semiconductors Table 83. HcRhStatus register: bit allocation Bit 31 Symbol CRWE Reset 0 Access R/W Bit 23 Symbol Reset 0 Access - Bit 15 Symbol DRWE Reset 0 Access R/W Bit 7 Symbol Reset 0 Access - Table 84. ...
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NXP Semiconductors Table 84. Bit 11.1.22 HcRhPortStatus[1:4] register (address: content of the base address register + 54h) The HcRhPortStatus[1:4] register is used to control and report port events on a per-port basis. NumberofDownstreamPort represents the ...
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NXP Semiconductors Table 86. Bit ISP1561_2 Product data sheet HCRhPortStatus[1:4] register: bit description Symbol Description - reserved PRSC Port Reset Status Change: This bit is set at the ...
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NXP Semiconductors Table 86. Bit ISP1561_2 Product data sheet HCRhPortStatus[1:4] register: bit description Symbol Description PPS On read Port Power Status: This bit reflects the port power status, regardless of the type of power ...
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NXP Semiconductors Table 86. Bit 11.2 USB legacy support registers The ISP1561 supports legacy keyboard and mouse. Four operational registers are used to provide the legacy support. Each of these registers is located on a 32-bit boundary. ...
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NXP Semiconductors Table 87. Offset 100h 104h 108h 10Ch Table 88. I/O address 60h 60h 64h 64h 11.2.1 HceControl register (address: content of the base address register + 100h) Table 89 Table 89. HceControl register: bit allocation Bit 31 Symbol ...
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NXP Semiconductors Table 90. Bit 11.2.2 HceInput register (address: content of the base address register + 104h) The HceInput register is a 4-byte register, and the bit allocation ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access - Bit 15 Symbol Reset 0 Access - Bit 7 Symbol Reset 0 Access R/W R/W Table 92. Bit 11.2.3 HceOutput register (address: content of the ...
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NXP Semiconductors Table 94. Bit 11.2.4 HceStatus register (address: content of the base address register + 10Ch) The contents of the HceStatus register are returned on an I/O read of port 64h when emulation ...
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NXP Semiconductors Table 96. Bit 11.3 EHCI controller capability registers Other than the OHCI Host Controller, there are some registers in EHCI that define the capability of EHCI. The address range of these registers is located before ...
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NXP Semiconductors Table 98. Bit 11.3.2 HCSPARAMS register (address: content of the base address register + 04h) The Host Controller Structural Parameters (HCSPARAMS) register is a set of fields that ...
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NXP Semiconductors Table 100. HCSPARAMS register: bit description Bit 11.3.3 HCCPARAMS register (address: content of the base address register + 08h) The Host Controller Capability Parameters ...
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NXP Semiconductors Bit 15 Symbol Reset 0 Access - Bit 7 Symbol Reset 0 Access R Table 102. HCCPARAMS register: bit description Bit 11.4 Operational registers of enhanced USB ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access - Bit 7 Symbol LHCR IAAD Reset 0 Access R/W R/W Table 104. USBCMD register: bit description Bit ...
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NXP Semiconductors Table 104. USBCMD register: bit description Bit ISP1561_2 Product data sheet Symbol Description IAAD Interrupt on Asynchronous Advance Doorbell: This bit is used as a doorbell by software to notify ...
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NXP Semiconductors 11.4.2 USBSTS register (address: content of the base address register + 10h) The USB Status (USBSTS) register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is ...
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NXP Semiconductors Table 106. USBSTS register: bit description Bit ISP1561_2 Product data sheet Symbol Description HCH HC Halted Default. This bit is logic 0 when the Run/Stop bit ...
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NXP Semiconductors 11.4.3 USBINTR register (address: content of the base address register + 14h) The USB Interrupt Enable (USBINTR) register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt ...
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NXP Semiconductors Table 108. USBINTR register: bit description Bit 11.4.4 FRINDEX register (address: content of the base address register + 18h) The Frame Index (FRINDEX) register is used by the Host Controller to index into the periodic ...
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NXP Semiconductors Table 110. FRINDEX register: bit description Bit Table 111. N based value of FLS[1:0] FLS[1:0] 00b 01b 10b 11b 11.4.5 CTRLDSSEGMENT register (address: content of the base address register + 1Ch) ...
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NXP Semiconductors Table 112. PERIODICLISTBASE register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access - Table ...
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NXP Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol LPL[2:0] Reset 0 Access - Table 115. ASYNCLISTADDR register: bit description Bit 11.4.8 CONFIGFLAG register (address: content of the base address ...
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NXP Semiconductors 11.4.9 PORTSC registers (address: content of the base address register + 50h + (4 times Port Number The Port Status and Control (PORTSC) register (bit allocation: auxiliary power well only reset by ...
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NXP Semiconductors Table 119. PORTSC register: bit description Bit PTC[3: PIC[1: LS[1:0] ISP1561_2 Product data sheet Symbol Description Port Test Control: Default = 0000b. When ...
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NXP Semiconductors Table 119. PORTSC register: bit description Bit ISP1561_2 Product data sheet Symbol Description - reserved PR Port Reset: Logic 1 means the port is in reset. Logic 0 means the port ...
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NXP Semiconductors Table 119. PORTSC register: bit description Bit [1] These fields read logic 0, if the Port Power (PP) (bit 12 in register PORTSC 1,2,3,4) is logic 0. ...
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NXP Semiconductors 12. Current consumption Table 120 SEL2PORTS pin is connected to V Table 120. Current consumption when SEL2PORTS is HIGH Cumulative current Total current on pins V plus AV AUX plus AV plus V AUX_PLL DD Auxiliary current on ...
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NXP Semiconductors Table 121. Current consumption when SEL2PORTS is LOW Cumulative current On pin V DD [1] When one to four full-speed or low-speed power devices are connected, the current consumption is comparable with the current consumption when no high-speed ...
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NXP Semiconductors 13. Limiting values Table 123. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V auxiliary voltage AUX AV analog auxiliary voltage (3.3 V); AUX supply voltage AV analog ...
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NXP Semiconductors 15. Static characteristics Table 125. Static characteristics 3 3 +85 C; unless otherwise specified. DD amb Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage ...
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NXP Semiconductors Table 128. Static characteristics: USB interface block (pins DM1 to DM4 and DP1 to DP4 3 3 +85 C; unless otherwise specified. DD amb Symbol Parameter V high-speed ...
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NXP Semiconductors 16. Dynamic characteristics Table 129. Dynamic characteristics: system clock timing +85 C; unless otherwise specified. DD amb Symbol Parameter Crystal oscillator f clock frequency clk External ...
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NXP Semiconductors Table 132. Dynamic characteristics: high-speed source electrical characteristics +85 C; unless otherwise specified. DD amb Symbol Parameter Z driver output impedance HSDRV (which also serves as ...
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NXP Semiconductors 16.1 Timing Table 135. PCI clock and IO timing Symbol Parameter PCI clock timing; see Figure 5 T CLK cycle time cyc t CLK HIGH time high t CLK LOW time low SR CLK slew rate CLK SR ...
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NXP Semiconductors CLK input delay Fig 6. PCI input timing CLK output delay output Fig 7. PCI output timing T PERIOD 3.3 V crossover point differential data lines the bit duration corresponding with the USB data ...
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NXP Semiconductors 17. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 pin 1 index 128 DIMENSIONS (mm are the original dimensions) A UNIT ...
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NXP Semiconductors 18. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction to soldering Soldering ...
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NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 10. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 138. Abbreviations Acronym DID EHCI EMI EOF HC HCCA ...
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NXP Semiconductors [3] ISP1561 Evaluation Board User’s Guide — UM10005 [4] Open Host Controller Interface Specification for USB — Rev. 1.0a [5] PCI Bus Power Management Interface Specification — Rev. 1.1 [6] PCI Local Bus Specification — Rev. 2.2 [7] ...
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NXP Semiconductors 21. Revision history Table 139. Revision history Document ID Release date ISP1561_2 20070305 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have ...
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NXP Semiconductors 22. Legal information 22.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . ...
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NXP Semiconductors Table 96. HceStatus register: bit description . . . . . . . . . .65 Table 97. CAPLENGTH/HCIVERSION register: bit allocation . . . . . . . . . . . . . . . . ...
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NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration ...
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NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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NXP Semiconductors 11.1.10 HcControlCurrentED register (address: content of the base address register + 24h 11.1.11 HcBulkHeadED register (address: content of the base address register + 28h ...