ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 59
ISP1561BMUM
Manufacturer Part Number
ISP1561BMUM
Description
IC USB HOST CTRL HI-SPD 128LQFP
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1561BMGE.pdf
(104 pages)
Specifications of ISP1561BMUM
Controller Type
USB Peripheral Controller
Interface
PCI
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
ISP1561BM-T
ISP1561BM-T
ISP1561BM-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
NXP Semiconductors
Table 85.
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcRhPortStatus[1:4] register: bit allocation
11.1.22 HcRhPortStatus[1:4] register (address: content of the base address
31
23
15
0
0
0
7
0
-
-
-
-
Table 84.
register + 54h)
The HcRhPortStatus[1:4] register is used to control and report port events on a per-port
basis. NumberofDownstreamPort represents the number of HcRhPortStatus registers that
are implemented in hardware. The lower word reflects the port status. The upper word
reflects status change bits. Some status bits are implemented with special write behavior.
If a transaction, token through handshake, is in progress when a write to change port
status occurs, the resulting port status change is postponed until the transaction
completes. Always write logic 0 to the reserved bits. The bit allocation of the register is
given in
Bit
14 to 2
1
0
reserved
reserved
30
22
14
0
0
0
6
0
-
-
-
-
Table
Symbol Description
-
OCI
LPS
HcRhStatus register: bit description
85.
reserved
Overcurrent Indicator: This bit reports overcurrent conditions when global
reporting is implemented. When set, an overcurrent condition exists. When
cleared, all power operations are normal. If the per-port overcurrent protection
is implemented, this bit is always logic 0.
On read Local Power Status: The root hub does not support the local power
status feature. Therefore, this bit is always read as logic 0.
On write Clear Global Power: In global power mode (Power Switching
Mode = 0), logic 1 is written to this bit to turn off power to all ports (clear Port
Power Status). In per-port power mode, it clears Port Power Status only on
ports whose Port Power Control Mask bit is not set. Writing logic 0 has no
effect.
29
21
13
0
0
0
5
0
-
-
-
-
reserved
Rev. 02 — 5 March 2007
PRSC
PRS
R/W
R/W
28
20
12
0
0
0
4
0
-
-
reserved
OCIC
POCI
R/W
R/W
27
19
11
0
0
0
3
0
-
-
…continued
PSSC
PSS
R/W
R/W
26
18
10
0
0
0
2
0
-
-
HS USB PCI Host Controller
PESC
LSDA
R/W
R/W
PES
R/W
25
17
0
0
9
0
1
0
-
© NXP B.V. 2007. All rights reserved.
ISP1561
CSC
CCS
PPS
R/W
R/W
R/W
58 of 103
24
16
0
0
8
0
0
0
-