ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 18

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
ISP1561_2
Product data sheet
Table 9.
Bit
15
14
13
12
11
10 to 9
8
7
6
5
4
3 to 0
Symbol
DPE
SSE
RMA
RTA
STA
DEVSELT[1:0]
MDPE
FBBC
-
66MC
CL
-
Status register: bit description
Rev. 02 — 5 March 2007
Description
Detected Parity Error: This bit must be set by the device whenever
it detects a parity error, even if the parity error handling is disabled.
Signaled System Error: This bit must be set whenever the device
asserts SERR#. Devices that never assert SERR# do not need to
implement this bit.
Received Master Abort: This bit must be set by a master device
whenever its transaction, except for special cycle, is terminated with
master abort. All master devices must implement this bit.
Received Target Abort: This bit must be set by a master device
whenever its transaction is terminated with target abort. All master
devices must implement this bit.
Signaled Target Abort: This bit must be set by a target device
whenever it terminates a transaction with target abort. Devices that
never signal target abort do not need to implement this bit.
DEVSEL Timing: These bits encode the timing of DEVSEL#. There
are three allowable timing for assertion of DEVSEL#:
00b — for fast
01b — for medium
10b — for slow
11b — is reserved
These bits are read-only and must indicate the slowest time that a
device asserts DEVSEL# for any bus command, except
Configuration Read and Configuration Write.
Master Data Parity Error: This bit is implemented by bus masters.
It is set when the following three conditions are met:
Fast Back-to-Back Capable: This read-only bit indicates whether
the target is capable of accepting fast back-to-back transactions
when the transactions are not to the same agent. This bit can be set
to logic 1 if the device can accept these transactions; and must be
set to logic 0 otherwise.
reserved
66 MHz Capable: This read-only bit indicates whether this device is
capable of running at 66 MHz. A value of logic 0 indicates 33 MHz,
and a value of logic 1 indicates 66 MHz.
Capabilities List: This read-only bit indicates whether this device
implements the pointer for a new capabilities linked list at offset 34h.
A value of logic 0 indicates that no new capabilities linked list is
available. A value of logic 1 indicates that the value read at offset
34h is a pointer in configuration space to a linked list of new
capabilities.
reserved
•
•
•
The bus agent asserted PERR# itself, on a read; or observed
PERR# asserted, on a write.
The agent setting the bit acted as the bus master for the
operation in which error occurred.
The Parity Error Response bit (in the Command register) is set.
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1561
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