ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 42

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
11.1.5 HcInterruptEnable register (address: content of the base address register +
reserved
7
0
-
Table 50.
10h)
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control
which events generate a hardware interrupt. If the following conditions occur:
Bit
31
30
29 to 7
6
5
4
3
2
1
0
•
•
•
A bit is set in the HcInterruptStatus register.
The corresponding bit in the HcInterruptEnable register is set.
The MIE (Master Interrupt Enable) bit is set.
RHSC
R/W
6
0
HcInterruptStatus register: bit description
Symbol
-
OC
-
RHSC
FNO
UE
RD
SF
WDH
SO
FNO
R/W
5
0
Rev. 02 — 5 March 2007
Description
reserved
Ownership Change: This bit is set by the Host Controller when HCD
sets the OCR (Ownership Change Request) field in
HcCommandStatus. This event, when unmasked, will always
immediately generate a System Management Interrupt (SMI). This bit
is forced to logic 0 when the SMI# pin is not implemented.
reserved
Root Hub Status Change: This bit is set when the content of
HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
Frame Number Overflow: This bit is set when the Most Significant Bit
(MSB) of HcFmNumber (bit 15) changes value, or after the
HccaFrameNumber is updated.
Unrecoverable Error: This bit is set when the Host Controller detects
a system error not related to USB. The Host Controller must not
proceed with any processing nor signaling before the system error is
corrected. The HCD clears this bit after the Host Controller is reset.
Resume Detected: This bit is set when the Host Controller detects
that a device on the USB is asserting resume signaling. It is the
transition from no resume signaling to resume signaling causing this
bit to be set. This bit is not set when the HCD sets the USBRESUME
state.
Start-of-Frame: At the start of each frame, this bit is set by the Host
Controller and an SOF token is generated at the same time.
Write-back Done Head: This bit is immediately set after the Host
Controller has written HcDoneHead to HccaDoneHead. Further,
updates of HccaDoneHead occur only after this bit is cleared. The
HCD must only clear this bit after it has saved the content of
HccaDoneHead.
Scheduling Overrun: This bit is set when USB schedules for current
frame overruns and after the update of HccaFrameNumber. A
scheduling overrun causes the SOC (Scheduling Overrun Count) of
HcCommandStatus to be incremented.
R/W
UE
4
0
R/W
RD
3
0
R/W
SF
2
0
HS USB PCI Host Controller
WDH
R/W
1
0
© NXP B.V. 2007. All rights reserved.
ISP1561
R/W
SO
41 of 103
0
0