ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 77

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
ISP1561_2
Product data sheet
11.4.5 CTRLDSSEGMENT register (address: content of the base address register +
11.4.6 PERIODICLISTBASE register (address: content of the base address
Table 110. FRINDEX register: bit description
Table 111. N based value of FLS[1:0]
1Ch)
The Control Data Structure Segment (CTRLDSSEGMENT) register corresponds to the
most significant address bits (bits 63 to 32) for all EHCI data structures. If the 64AC (64-bit
Addressing Capability) field in HCCPARAMS is cleared, then this register is not used and
software cannot write to it (reading from this register returns zero).
If the 64AC (64-bit Addressing Capability) field in HCCPARAMS is set, this register is used
with link pointers to construct 64-bit addresses to EHCI control data structures. This
register is concatenated with the link pointer from either the PERIODICLISTBASE,
ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address.
This register allows the host software to locate all control data structures within the same
4 GB memory segment.
register + 20h)
The Periodic Frame List Base Address (PERIODICLISTBASE) register contains the
beginning address of the periodic frame list in the system memory. If the Host Controller is
in 64-bit mode, as indicated by logic 1 in the 64AC (64-bit Addressing Capability) field in
the HCCPARAMS register, the most significant 32 bits of every control data structure
address comes from the CTRLDSSEGMENT register. The system software loads this
register before starting the schedule execution by the Host Controller. The memory
structure referenced by this physical memory pointer is assumed as 4 kB aligned. The
contents of this register are combined with the FRINDEX register to enable the Host
Controller to step through the periodic frame list in sequence. The bit allocation is given in
Table
Bit
31 to 14 -
13 to 0
FLS[1:0]
00b
01b
10b
11b
112.
Symbol
FRINDEX [13:0]
Rev. 02 — 5 March 2007
Description
reserved
Frame Index: Bits in this register are used for the frame number in
the SOF packet and as the index into the frame list. The value in this
register increments at the end of each time frame. For example,
micro frame. The bits used for the frame number in the SOF token
are taken from bits 13 to 3 of this register. Bits N to 3 are used for the
frame list current index. This means that each location of the frame
list is accessed eight times, frames or micro frames, before moving
to the next index.
FLS (Frame List Size) field in the USBCMD register.
Number elements
1024
512
256
reserved
Table 111
illustrates N based on the value of the
HS USB PCI Host Controller
N
12
11
10
-
© NXP B.V. 2007. All rights reserved.
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