ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 72

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
ISP1561_2
Product data sheet
Table 104. USBCMD register: bit description
Bit
6
5
4
3 to 2
1
0
Symbol Description
IAAD
ASE
PSE
FLS[1:0] Frame List Size: Default = 00b. This field is read and write only if PFLF (bit 1)
HC
RESET
RS
Interrupt on Asynchronous Advance Doorbell: This bit is used as a
doorbell by software to notify the Host Controller to issue an interrupt the next
time it advances the asynchronous schedule. Software must write logic 1 to
this bit to ring the doorbell. When the Host Controller has evicted all
appropriate cached schedule states, it sets the IAA (Interrupt on
Asynchronous Advance) status bit in the USBSTS register. If the IAAE
(Interrupt on Asynchronous Advance Enable) bit in the USBINTR register is
logic 1, then the Host Controller will assert an interrupt at the next interrupt
threshold. The Host Controller sets this bit to logic 0 after it sets IAA (Interrupt
on Asynchronous Advance) status bit in the USBSTS register. Software must
not set this bit when the asynchronous schedule is inactive because this
results in an undefined value.
Asynchronous Schedule Enable: Default = 0. This bit controls whether the
Host Controller skips processing the asynchronous schedule.
0 — Do not process the asynchronous schedule
1 — Use the ASYNCLISTADDR register to access the asynchronous
schedule
Periodic Schedule Enable: Default = 0. This bit controls whether the Host
Controller skips processing the periodic schedule.
0 — Do not process the periodic schedule
1 — Use the PERIODICLISTBASE register to access the periodic schedule
in the HCCPARAMS register is set to logic 1. This field specifies the size of the
frame list. The size the frame list controls which bits in the Frame Index
register must be used for the frame list current index.
00b — 1024 elements (4096 bytes)
01b — 512 elements (2048 bytes)
10b — 256 elements (1024 bytes) for small environments
11b — reserved
Host Controller Reset: This control bit is used by the software to reset the
Host Controller. The effects of this on Root Hub registers are similar to a chip
hardware reset. Setting this bit causes the Host Controller to reset its internal
pipelines, timers, counters, state machines, and so on, to their initial values.
Any transaction currently in progress on USB is immediately terminated. A
USB reset is not driven on downstream ports. This reset does not affect PCI
Configuration registers. All operational registers, including port registers and
port state machines, are set to their initial values. Port ownership reverts to the
companion Host Controller(s). The software must re-initialize the Host
Controller to return it to an operational state. This bit is cleared by the Host
Controller when the reset process is complete. Software cannot terminate the
reset process early by writing logic 0 to this register. Software must check the
HCH (HC Halted) bit in the USBSTS register is logic 0 before setting this bit.
Attempting to reset an actively running Host Controller results in undefined
behavior.
Run/Stop: 1 = Run. 0 = Stop. When set, the Host Controller executes the
schedule. The Host Controller continues execution as long as this bit is set.
When this bit is cleared, the Host Controller completes the current and active
transactions in the USB pipeline, and then halts. The HCH (HC Halted) bit in
the USBSTS register indicates when the Host Controller has finished the
transaction and has entered the stopped state. Software must check HCH (HC
Halted) in the USBSTS register is logic 1, before setting this bit.
Rev. 02 — 5 March 2007
…continued
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1561
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