ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 38

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
ISP1561_2
Product data sheet
Table 46.
Bit
31 to 11
10
9
8
7 to 6
5
HcControl register: bit description
Symbol
-
RWE
RWC
IR
HCFS[1:0]
BLE
Rev. 02 — 5 March 2007
Description
reserved
Remote Wake-up Enable: This bit is used by the HCD to enable or
disable the remote wake-up feature on detecting upstream resume
signaling. When this bit and the RD bit in HcInterruptStatus are set, a
remote wake-up is signaled to the host system. Setting this bit has no
impact on the generation of hardware interrupt.
Remote Wake-up Connected: This bit indicates whether the Host
Controller supports remote wake-up signaling. If remote wake-up is
supported and used by the system, it is the responsibility of the system
firmware to set this bit during POST. The Host Controller clears the bit on
a hardware reset but does not alter it on a software reset. Remote
wake-up signaling of the host system is host-bus-specific and is not
described in this specification.
Interrupt Routing: This bit determines the routing of interrupts
generated by events registered in HcInterruptStatus. If clear, all
interrupts are routed to the normal host bus interrupt mechanism. If set,
interrupts are routed to the system management interrupt. The HCD
clears this bit on a hardware reset, but it does not alter this bit on a
software reset. The HCD uses this bit as a tag to indicate the ownership
of the Host Controller.
Host Controller Functional State for USB:
00b — USBRESET
01b — USBRESUME
10b — USBOPERATIONAL
11b — USBSUSPEND
A transition to USBOPERATIONAL from another state causes SOF
generation to begin 1 ms later. The HCD may determine whether the
Host Controller has begun sending SOFs by reading the SF field of
HcInterruptStatus.
This field may be changed by the Host Controller only when in the
USBSUSPEND state. The Host Controller may move from the
USBSUSPEND state to the USBRESUME state after detecting the
resume signaling from a downstream port.
The Host Controller enters USBSUSPEND after a software reset; it
enters USBRESET after a hardware reset. The latter also resets the root
hub and asserts subsequent reset signaling to downstream ports.
Bulk List Enable: This bit is set to enable the processing of the bulk list
in the next frame. If cleared by the HCD, processing of the bulk list does
not occur after the next SOF. The Host Controller checks this bit
whenever it wants to process the list. When disabled, the HCD may
modify the list. If HcBulkCurrentED is pointing to an Endpoint Descriptor
(ED) to be removed, the HCD must advance the pointer by updating
HcBulkCurrentED before re-enabling processing of the list.
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1561
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