ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 60

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
ISP1561_2
Product data sheet
Table 86.
Bit
31 to 21
20
19
18
17
16
15 to 10
9
Symbol Description
-
PRSC
OCIC
PSSC
PESC
CSC
-
LSDA
HCRhPortStatus[1:4] register: bit description
reserved
Port Reset Status Change: This bit is set at the end of the 10 ms port reset
signal. The HCD can write logic 1 to clear this bit. Writing logic 0 has no
effect.
0 — Port reset is not complete
1 — Port reset is complete
Port Overcurrent Indicator Change: This bit is valid only if overcurrent
conditions are reported on a per-port basis. This bit is set when the root hub
changes the POCI (Port Overcurrent Indicator) bit. The HCD can write logic 1
to clear this bit. Writing logic 0 has no effect.
0 — No change in Port Overcurrent Indicator
1 — POCI has changed
Port Suspend Status Change: This bit is set when the full resume
sequence is completed. This sequence includes the 20 ms resume pulse, LS
EOP and 3 ms re-synchronization delay. The HCD can write logic 1 to clear
this bit. Writing logic 0 has no effect. This bit is also cleared when Reset
Status Change is set.
0 — Resume is not completed
1 — Resume is completed
Port Enable Status Change: This bit is set when hardware events cause the
PES (Port Enable Status) bit to be cleared. Changes from the HCD writes do
not set this bit. The HCD can write logic 1 to clear this bit. Writing logic 0 has
no effect.
0 — No change in PES
1 — Change in PES
Connect Status Change: This bit is set whenever a connect or disconnect
event occurs. The HCD can write logic 1 to clear this bit. Writing logic 0 has
no effect. If CCS (Current Connect Status) is cleared when a Set Port Reset,
Set Port Enable or Set Port Suspend write occurs, this bit is set to force the
driver to re-evaluate the connection status because these writes must not
occur if the port is disconnected.
0 — No change in CCS
1 — Change in CCS
Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a
root hub reset to inform the system that the device is attached.
reserved
On read Low-speed Device Attached: This bit indicates the speed of the
device attached to this port. When set, a low-speed device is attached to this
port. When cleared, a full-speed device is attached to this port. This field is
valid only when the CCS is set.
0 — Port is not suspended
1 — Port is suspended
On write Clear Port Power: The HCD can clear the PPS (Port Power Status)
bit by writing logic 1 to this bit. Writing logic 0 has no effect.
Rev. 02 — 5 March 2007
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1561
59 of 103