ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 26

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 33.
Table 34.
[1]
[2]
ISP1561_2
Product data sheet
Bit
7 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
X is 0 for OHCI1, OHCI2 and EHCI S1; X is 1 for EHCI S3.
X is 0 for OHCI1 and OHCI2; X is 1 for EHCI.
Symbol
NEXT_ITEM_
PTR[7:0]
NEXT_ITEM_PTR register: bit description
PMC register: bit allocation
8.2.3.2 NEXT_ITEM_PTR register (address: value read from address 34h + 1h)
8.2.3.3 PMC register (address: value read from address 34h + 2h)
X
15
R
R
7
0
[1]
AUX_C[2:0]
The Next Item Pointer (NEXT_ITEM_PTR) register (see
of the next item in the function’s capability list. The value given is an offset into the
function’s PCI configuration space. If the function does not implement any other
capabilities defined by the PCI-SIG for inclusion in the capabilities list, or if power
management is the last item in the list, then this register must be set to 00h.
The Power Management Capabilities (PMC) register is a 2-byte register, and the bit
allocation is given in
capabilities of the function related to power management.
Table 35.
Bit
15 to 11
10
9
Access
R
14
R
R
1
6
0
PMC register: bit description
Symbol
PME_S[4:0]
D2_S
D1_S
PME_S[4:0]
Value
00h
DSI
X
13
R
R
5
0
[2]
Table
Rev. 02 — 5 March 2007
Description
Next Item Pointer: This field provides an offset into the function’s
PCI configuration space pointing to the location of the next item in the
function’s capability list. If there are no additional items in the
capabilities list, this register is set to 00h.
34. This read-only register provides information on the
Description
PME Support: This 5-bit field indicates the power states in which
the function may assert PME#. Logic 0 for any bit indicates that
the function is not capable of asserting the PME# signal while in
that power state.
PME_S[0] — PME# can be asserted from D0
PME_S[1] — PME# can be asserted from D1
PME_S[2] — PME# can be asserted from D2
PME_S[3] — PME# can be asserted from D3
PME_S[4] — PME# can be asserted from D3
D2 Support: If this bit is logic 1, this function supports the D2
power management state. Functions that do not support D2 must
always return a value of logic 0 for this bit.
D1 Support: If this bit is logic 1, this function supports the D1
power management state. Functions that do not support D1 must
always return a value of logic 0 for this bit.
reserved
12
R
1
4
0
-
PMI
X
11
R
R
3
0
[2]
D2_S
Table
X
10
R
R
2
0
[2]
HS USB PCI Host Controller
33) describes the location
VER[2:0]
D1_S
R
9
1
R
hot
cold
1
1
© NXP B.V. 2007. All rights reserved.
ISP1561
AUX_C[2:0]
X
25 of 103
R
8
R
[2]
0
0