ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 70

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 103. USBCMD register: bit allocation
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
11.4.1 USBCMD register (address: content of the base address register + 0Ch)
11.4 Operational registers of enhanced USB Host Controller
15
31
R
0
7
0
0
-
-
Table 102. HCCPARAMS register: bit description
The USB Command (USBCMD) register indicates the command to be executed by the
serial Host Controller. Writing to this register causes a command to be executed.
Table 103
Bit
31 to 8
7 to 4
3 to 2
1
0
14
30
R
0
6
0
0
-
-
Symbol
-
IST[3:0]
-
PFLF
64AC
shows the USBCMD register bit allocation.
IST[3:0]
13
29
R
0
5
0
0
-
-
Rev. 02 — 5 March 2007
Description
reserved
Isochronous Scheduling Threshold: Default = implementation
dependent. This field indicates, relative to the current position of the
executing Host Controller, where software can reliably update the
isochronous schedule. When IST[3] is logic 0, the value of the least
significant three bits indicates the number of micro frames a Host
Controller can hold a set of isochronous data structures, one or more,
before flushing the state. When IST[3] is logic 1, then host software
assumes the Host Controller may cache an isochronous data structure
for an entire frame.
reserved
Programmable Frame List Flag: Default = implementation
dependent. If this bit is cleared, the system software must use a frame
list length of 1024 elements with this Host Controller. The USBCMD
register FLS (Frame List Size) field is a read-only register and must be
cleared. If PFLF is set, the system software can specify and use a
smaller frame list and configure the host through the USBCMD register
FLS field. The frame list must always be aligned on a 4 kB page
boundary to ensure that the frame list is always physically contiguous.
64-bit Addressing Capability: This field documents the addressing
range capability.
0 — Data structures using 32-bit address memory pointers
1 — Data structures using 64-bit address memory pointers
12
28
R
0
4
1
0
-
-
reserved
reserved
11
27
0
3
0
0
-
-
-
reserved
10
26
0
2
0
0
-
-
-
HS USB PCI Host Controller
PFLF
25
R
9
0
1
1
0
-
-
© NXP B.V. 2007. All rights reserved.
ISP1561
64AC
69 of 103
24
R
8
0
0
0
0
-
-