ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 41

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 49.
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptStatus register: bit allocation
11.1.4 HcInterruptStatus register (address: content of the base address register +
reserved
31
23
15
0
0
0
-
-
-
Table 48.
0Ch)
This is a 4-byte register that provides the status of the events that cause hardware
interrupts. The bit allocation of the register is given in
Host Controller sets the corresponding bit in this register. When a bit becomes set, a
hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register
(see
specific bits in this register by writing logic 1 to the bit positions to be cleared. The HCD
may not set any of these bits. The Host Controller does not clear the bit.
Bit
1
0
Table
R/W
OC
30
22
14
0
0
0
-
-
HcCommandStatus register: bit description
51) and the MIE (Master Interrupt Enable) bit is set. The HCD may clear
Symbol
CLF
HCR
29
21
13
0
0
0
-
-
-
Description
Control List Filled: This bit is used to indicate whether there are any TDs
on the control list. It is set by the HCD whenever it adds a TD to an ED in
the control list.
When the Host Controller begins to process the head of the control list, it
checks CLF. If CLF is logic 0, the Host Controller does not need to
process the control list. If Control-Filled (CF) is logic 1, the Host Controller
must start processing the control list and set CLF to logic 0. If the Host
Controller finds a TD on the list, then the Host Controller must set CLF to
logic 1, causing the control list processing to continue. If no TD is found
on the control list, and if the HCD does not set CLF, then CLF is still
logic 0 when the Host Controller completes processing the control list and
the control list processing stops.
Host Controller Reset: This bit is set by the HCD to initiate a software
reset of the Host Controller. Regardless of the functional state of the Host
Controller, it moves to the USBSUSPEND state in which most of the
operational registers are reset, except those stated otherwise; for
example, the IR (Interrupt Routing) field of HcControl, and no host bus
accesses are allowed. This bit is cleared by the Host Controller on
completing the reset operation. The reset operation must be completed
within 10 s. This bit, when set, must not cause a reset to the root hub
and no subsequent reset signaling must be asserted to its downstream
ports.
Rev. 02 — 5 March 2007
28
20
12
0
0
0
-
-
-
reserved
reserved
27
19
11
0
0
0
-
-
-
reserved
Table
…continued
26
18
10
0
0
0
-
-
-
49. When an event occurs, the
HS USB PCI Host Controller
25
17
0
0
9
0
-
-
-
© NXP B.V. 2007. All rights reserved.
ISP1561
40 of 103
24
16
0
0
8
0
-
-
-