isp1583 NXP Semiconductors, isp1583 Datasheet

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isp1583

Manufacturer Part Number
isp1583
Description
Hi-speed Universal Serial Bus Peripheral Controller
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
The ISP1583 is a cost-optimized and feature-optimized Hi-Speed Universal Serial Bus
(USB) Peripheral Controller. It fully complies with
Specification Rev.
(12 Mbit/s).
The ISP1583 provides high-speed USB communication capacity to systems based on
microcontrollers or microprocessors. It communicates with a microcontroller or
microprocessor of a system through a high-speed general-purpose parallel interface.
The ISP1583 supports automatic detection of Hi-Speed USB system operation. Original
USB fall-back mode allows the device to remain operational under full-speed conditions. It
is designed as a generic USB Peripheral Controller so that it can fit into all existing device
classes, such as imaging class, mass storage devices, communication devices, printing
devices and human interface devices.
The ISP1583 is a low-voltage device, which supports I/O pad voltages from 1.65 V to
3.6 V.
The internal generic Direct Memory Access (DMA) block allows easy integration into data
streaming applications. In addition, the various configurations of the DMA block are
tailored for mass storage applications.
The modular approach to implementing a USB Peripheral Controller allows the designer
to select the optimum system microcontroller from the wide variety available. The ability to
reuse existing architecture and firmware shortens the development time, eliminates risk
and reduces cost. The result is fast and efficient development of the most cost-effective
USB peripheral solution.
The ISP1583 also incorporates features such as SoftConnect, a reduced frequency
crystal oscillator, and integrated termination resistors. These features allow significant
cost savings in system design and easy implementation of advanced USB functionality
into PC peripherals.
I
I
I
ISP1583
Hi-Speed Universal Serial Bus Peripheral Controller
Rev. 06 — 20 August 2007
Complies fully with:
Supports data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s)
Direct interface to ATA/ATAPI peripherals; applicable only in split bus mode
N
N
N
Ref. 1 “Universal Serial Bus Specification Rev. 2.0”
Most device class specifications
ACPI, OnNow and USB power management requirements
2.0”, supporting data transfer at high-speed (480 Mbit/s) and full-speed
Ref. 1 “Universal Serial Bus
Product data sheet

Related parts for isp1583

isp1583 Summary of contents

Page 1

... USB Peripheral Controller so that it can fit into all existing device classes, such as imaging class, mass storage devices, communication devices, printing devices and human interface devices. The ISP1583 is a low-voltage device, which supports I/O pad voltages from 1. 3.6 V. The internal generic Direct Memory Access (DMA) block allows easy integration into data streaming applications. In addition, the various confi ...

Page 2

... I 3G mobile phone I MP3 player I Communication device, for example: router and modem I Printer I Scanner ISP1583_6 Product data sheet sensing BUS Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller Ref. 2 “On-The-Go ) BUS © NXP B.V. 2007. All rights reserved 100 ...

Page 3

... ISP1583ET1 TFBGA64 plastic thin fine-pitch ball grid array package; 64 balls; body 4 ISP1583_6 Product data sheet 9 0.85 mm Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller Version SOT804-1 6 0.8 mm SOT543-1 4 0.8 mm SOT969-1 © ...

Page 4

... AGND SUSPEND WAKEUP VCC1V8 The figure shows the ISP1583BS pinout. For the ISP1583ET and ISP1583ET1 ballouts, see The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Configuration register). (1) Pin 15 is shared by READY and IORDY. ...

Page 5

... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration ISP1583BS (top view) Fig 3. Pin configuration ISP1583ET (top view) ISP1583_6 Product data sheet terminal 1 index area AGND 1 2 RPU AGND 6 RREF 7 RESET_N 8 EOT DREQ 9 10 DACK DIOR 11 DIOW 12 DGND ...

Page 6

... NXP Semiconductors Fig 4. Pin configuration ISP1583ET1 (top view) 6.2 Pin description Table 2. Pin description [1] Symbol Pin ISP1583BS ISP1583ET ISP1583ET1 AGND 1 D2 RPU AGND 5 - RREF 6 D1 RESET_N 7 E2 EOT 8 E1 DREQ 9 F2 ISP1583_6 Product data sheet ISP1583ET1 ball A1 ...

Page 7

... LOW: the ISP1583 is processing a previous command or data and is not ready for the next command or data transfer • HIGH: the ISP1583 is ready for the next microprocessor read or write I/O ready input — Used in split bus mode to access ATA/ATAPI peripherals (PIO mode only) bidirectional pad slew-rate control; TTL ...

Page 8

... NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET ISP1583ET1 [3] DA2 17 J2 CS_N 18 K2 RW_N/RD_N 19 J3 DS_N/WR_N 20 K3 [3] CS0_N 21 J4 [3] CS1_N 22 K4 AD0 23 K5 AD1 24 J5 AD2 CC(I/O) AD3 27 K7 AD4 28 J7 AD5 29 K8 ISP1583_6 Product data sheet ...

Page 9

... NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET ISP1583ET1 AD6 30 J8 AD7 31 K9 [4] VCC1V8 32 K10 n. MODE1 34 J10 DGND 35 H9 ALE/A0 36 H10 DATA0 37 G9 DATA1 38 G10 DATA2 39 F9 DATA3 40 F10 ISP1583_6 Product data sheet [2] Type Description H6 I/O bit 6 of the multiplexed address and data bus bidirectional pad ...

Page 10

... NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET ISP1583ET1 [ CC(I/O) DATA4 42 E10 DATA5 43 D10 DATA6 44 D9 DATA7 45 C10 DATA8 46 C9 DATA9 47 B10 DATA10 48 A10 DATA11 49 A9 DATA12 50 B8 DATA13 51 A8 DATA14 52 B7 DATA15 CC(I/O) ISP1583_6 Product data sheet ...

Page 11

... NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET ISP1583ET1 BUS [4] VCC1V8 56 A6 XTAL2 57 A5 XTAL1 58 A4 DGND 59 B4 [3] MODE0/DA1 CC(3V3) ISP1583_6 Product data sheet [2] Type Description A6 A USB bus power sensing input — Used to detect whether the host is connected or not ...

Page 12

... NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET ISP1583ET1 BUS_CONF [3] DA0 WAKEUP 63 A2 SUSPEND 64 C2 DGND - B9 DGND exposed die J9 pad [1] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals. [2] All outputs and I/O pins can source 4 mA, unless otherwise specified. ...

Page 13

... Optional double buffering increases the data throughput of these data endpoints. The ISP1583 requires 3.3 V power supply. It has 5 V tolerant I/O pads and an internal 1.8 V regulator to power the digital logic. The I/O voltage can range from 1. 3.6 V. ISP1583_6 ...

Page 14

... NXP Semiconductors The ISP1583 operates MHz crystal oscillator. An integrated 40 multiplier generates the internal sampling clock of 480 MHz. 7.1 DMA interface, DMA handler and DMA registers The DMA block can be subdivided into two blocks: DMA handler and DMA interface. The firmware writes to the DMA Command register to start a DMA transfer (see The command opcode determines whether a generic DMA, Parallel I/O (PIO) or Multi-word DMA (MDMA) transfer will start ...

Page 15

... The ISP1583 handles more than one electrical state, Full-Speed (FS) or High-Speed (HS), under the USB specification. When the USB cable is connected from the peripheral to the Host Controller, the ISP1583 defaults to the FS state, until it sees a bus reset from the Host Controller. ISP1583_6 Product data sheet ...

Page 16

... DP and DM lines. Remark: If there are any erroneous unwanted pulses or glitches detected by the ISP1583 DP and DM lines, there is a possibility of the ISP1583 clocking this state into the internal core, causing unknown behaviors. 7.7 NXP Serial Interface Engine (SIE) The NXP SIE implements the full USB protocol layer completely hardwired for speed and needs no fi ...

Page 17

... Assign Control Function register = 10h 7.10 Reconfiguring endpoints The ISP1583 endpoints have a limitation when implementing a composite device with at least two functionalities that require the support of alternate settings, for example, the video class and audio class devices. The ISP1583 endpoints cannot be reconfigured on the fl ...

Page 18

... Plug-in: the USB cable is being plugged in, and V 7.14 Interrupt 7.14.1 Interrupt output pin The Interrupt Configuration register of the ISP1583 controls the behavior of the INT output pin. The polarity and signaling mode of the INT pin can be programmed by setting bits INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see GLINTENA of the Mode register (R/W: 0Ch) is used to enable pin INT ...

Page 19

... INT signals for the IN pipe. Field DDBGMODOUT[1:0] of the Interrupt Configuration register controls the generation of INT signals for the OUT pipe; see Table ISP1583_6 Product data sheet 27. Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller © NXP B.V. 2007. All rights reserved 100 ...

Page 20

DMA Interrupt Reason register GDMA_STOP EXT_EOT INT_EOT BSY_DONE TF_RD_DONE CMD_INTRQ_OK OR DMA Interrupt Enable register IE_GDMA_STOP IE_EXT_EOT IE_INT_EOT IE_BSY_DONE IE_TF_RD_DONE IE_CMD_INTRQ_OK Fig 5. Interrupt logic Interrupt Enable register IEBRST IESOF IEDMA IEP7RX IEP7TX Interrupt register BRESET SOF DMA EP7RX EP7TX ...

Page 21

... SOF asserted) Pin INT: HIGH = de-assert; LOW = assert (individual interrupts are enabled). pin is one of the ways to wake up the clock when the ISP1583 is suspended Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller Section 8.2.2, Section 8.2.5 ...

Page 22

... Fig 8. Oscilloscope reading: no resistor and capacitor in the network Fig 9. Oscilloscope reading: with resistor and capacitor in the network ISP1583_6 Product data sheet 55 ISP1583 The figure shows the ISP1583BS pinout. For the ISP1583ET and ISP1583ET1 ballouts, see Table 2. Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller USB 1 µ ...

Page 23

... NXP Semiconductors 7.16 Power-on reset The ISP1583 requires a minimum pulse width of 500 s. The RESET_N pin can either be connected to V externally controlled (by the microcontroller, ASIC, and so on). When V connected to the RESET_N pin, the internal pulse width t The power-on reset function can be explained by viewing the dips and the V t0 — ...

Page 24

... VCC1V8 output. If the ripple voltage at the input is higher than 20 mV, then use 4.7 F LOW ESR capacitors (ESR from 0.2 high-speed signal quality at the USB side. The figure shows the ISP1583BS pinout. For the ISP1583ET and ISP1583ET1 ballouts, see Table 2. shows power modes in which the ISP1583 can be operated. ...

Page 25

... V this, implement external V be connected to pin GPIO of the processor to qualify the interrupt from the ISP1583. Remark: When the core power is applied, the ISP1583 must be reset using the RESET_N pin. The minimum width of the reset pulse width must be 2 ms. ...

Page 26

... Table 9. ISP1583 operation Back voltage is not measured in this mode Back voltage is not an issue because core power is lost Table 10. ISP1583 operation SRP is not applicable OTG is not possible because V present and so core power is lost ISP1583_6 Product data sheet Operation truth table for SoftConnect ...

Page 27

... NXP Semiconductors 7.17.2 Self-powered mode Fig 15. Self-powered mode In self-powered mode, V Table 11. ISP1583 operation Normal bus operation No pull [1] When the USB cable is removed, SoftConnect is disabled. Table 12. ISP1583 operation Clock will wake up: After a resume and After a bus reset Clock will wake up: After detecting the presence of V Table 13 ...

Page 28

... SRP is possible 7.17.3 Bus-powered mode 1. 3.3 V Fig 16. Bus-powered mode In bus-powered mode (see the 5 V-to-3.3 V voltage regulator. The input to the regulator is from V USB cable, the ISP1583 goes through the power-on reset cycle. In this mode, OTG is disabled. Table 15. ISP1583 operation Normal bus operation Power is lost Table 16 ...

Page 29

... NXP Semiconductors Table 17. ISP1583 operation Back voltage is not measured in this mode Power is lost Table 18. ISP1583 operation SRP is not applicable Power is lost ISP1583_6 Product data sheet Operation truth table for back voltage compliance V CC(3V3) 3 Operation truth table for OTG V CC(3V3) 3 Rev. 06 — ...

Page 30

... ATA configuration (IORDY enable, mode selection: ATA, MDMA, PIO) 3Ch endian type, master or slave selection, signal polarity for DACK, DREQ, DIOW, DIOR, EOT Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller Size Reference (bytes) 1 Section 8.2.1 on page 32 2 Section 8 ...

Page 31

... DP and DM states, internal transceiver test (PHY) Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller Size Reference (bytes) 2 Section 8.4.5 on page ...

Page 32

... DEVADDR[6:0] Device Address: This field specifies the USB device address. Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller 3 2 DEVADDR[6: R/W R/W R/W Table 22). ISP1583 Table R/W © NXP B.V. 2007. All rights reserved 100 ...

Page 33

... GOSUSP Go Suspend: Writing logic 1, followed by logic 0 will activate suspend mode. SFRESET Soft Reset: Writing logic 1, followed by logic 0 will enable a software-initiated reset to the ISP1583. A soft reset is similar to a hardware-initiated reset (using the RESET_N pin). Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller 11 ...

Page 34

... PWRON Power On: The SUSPEND pin output control. 0 — The SUSPEND pin is HIGH when the ISP1583 is in the suspend state. Otherwise, the SUSPEND pin is LOW. 1 — When the device is woken up from the suspend state, there will active HIGH pulse on the SUSPEND pin. The SUSPEND pin will remain LOW in all other states ...

Page 35

... Table 27 DDBGMODOUT interrupt on all ACK, NYET and NAK interrupt on ACK and NYET interrupt on all ACK, NYET [1] and first NAK Table 28 INITCOND DISCV R/W R/W R/W © NXP B.V. 2007. All rights reserved. ISP1583 0 INTPOL 0 unchanged R/W Table 27 [1] 0 OTG 100 ...

Page 36

... Once set, it remains at logic 1. To clear this bit, write logic 1. (The ISP1583 continuously updates this bit to logic 1 when the B-session is valid. If the B-session is valid after it is cleared set back to logic 1 by the ISP1583). 0 — It implies that SRP has failed. To proceed to a normal operation, the device can restart SRP, clear bit OTG or proceed to an error handling process. 1 — ...

Page 37

... NXP Semiconductors 8.2.4.1 Session Request Protocol (SRP) The ISP1583 can initiate an SRP. The B-device initiates SRP by data-line pulsing, followed by V pulsing. The ISP1583 can initiate the B-device SRP by performing the following steps: 1. Set the OTG bit to start SRP. 2. Detect initial conditions by following the instructions given in bit INITCOND of the OTG register ...

Page 38

... Hi-Speed USB Peripheral Controller IEP7TX - - R IEP4TX IEP4RX IEP3TX R/W R/W R IEP0TX IEP0RX reserved R/W R IESUSP IEPSOF IESOF R/W R/W R/W © NXP B.V. 2007. All rights reserved. ISP1583 24 IEP7RX 0 0 R/W 16 IEP3RX 0 0 R/W 8 IEP0SETUP 0 0 R/W 0 IEBRST 100 ...

Page 39

... Logic 1 enables interrupt on detecting a pseudo SOF. IESOF Logic 1 enables interrupt on detecting an SOF. IEBRST Logic 1 enables interrupt on detecting a bus reset EP0SETUP - R/W R/W Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller …continued sensing. BUS ENDPIDX[3: R/W R/W R/W © NXP B.V. 2007. All rights reserved. ...

Page 40

... R/W Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller ENDPIDX DIR 00h 0 00h 0 00h 1 0Xh 0 0Xh 1 Table 35. Register bits can stall, clear VENDP DSEN STATUS R/W W R/W © NXP B.V. 2007. All rights reserved. ISP1583 0 STALL 100 ...

Page 41

... After the completion of the set-up stage, firmware must determine whether a data stage is required. For control OUT, firmware will set this bit and the ISP1583 goes into the data stage. Otherwise, the ISP1583 will NAK the data stage transfer. For control IN, firmware will set this bit before writing data to the TX FIFO and validate the endpoint data stage is required, fi ...

Page 42

... DATAPORT[7:0] data (lower byte) Table Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller R/W R/W R R/W R/W R/W 39. Table 43). A smaller value can be written when ISP1583 R R/W © NXP B.V. 2007. All rights reserved 100 ...

Page 43

... R/W R DATACOUNT[7: R/W R/W Buffer Length register: bit description Symbol Description DATACOUNT[15:0] Data Count: Determines the current packet size of the indexed endpoint FIFO. Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller R/W R/W R ...

Page 44

... One of the buffers is filled. 10 — One of the buffers is filled. 11 — Both the buffers are filled NTRANS[1: R FFOSZ[7: R/W R/W Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller BUF1 - - Table 43 FFOSZ[10: R/W R/W ...

Page 45

... Table 44. Bit The ISP1583 supports all the transfers given in Rev. 2.0”. Each programmable FIFO can be independently configured using its Endpoint MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN plus OUT), including set-up token buffer, control IN and control OUT, must not exceed 8192 bytes ...

Page 46

... MSByte is written. Once the DMA transfer is started, the transfer counter starts decrementing and on reaching 0, bit DMA_XFER_OK is set and an interrupt is generated by the ISP1583. If the DMA master wishes to terminate the DMA transfer, it can issue an EOT signal to the ISP1583. This EOT signal overrides the transfer counter and can terminate the DMA transfer at any time ...

Page 47

... MDMA (master) read/write (opcode = 06h/07h) — Generic DMA master mode. Depending on the MODE[1:0] bits set in the DMA Configuration register, the DACK, DIOR or DIOW signal strobes data. These signals are driven by the ISP1583. In master mode, BURSTCOUNTER[12:0] in the DMA Burst Counter register, DIS_XFER_CNT in the DMA Confi ...

Page 48

... Description DMA_CMD[7:0] DMA command code, see PIO Read or Write that started using DMA Command register only performs a 16-bit transfer. Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller …continued MDMA (master) read/write (opcode = 06h/07h) determines whether data byte swapped or normal; ...

Page 49

... DMA reset. MDMA stop MDMA stop: This command immediately stops the MDMA data transfer. This is applicable for commands 06h and 07h only. Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller © NXP B.V. 2007. All rights reserved 100 ...

Page 50

... This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates the remaining number of bytes left for transfer. The bit allocation is given in For IN endpoint — Because there is a FIFO in the ISP1583 DMA controller, some data may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and the maximum delay time for data to be shifted to endpoint buffer is 60 ns. For OUT endpoint — ...

Page 51

... DMA Transfer Counter register: bit description Symbol DMACR4 = DMACR[31:24] DMACR3 = DMACR[23:16] DMACR2 = DMACR[15:8] DMACR1 = DMACR[7: ATA_ DMA_MODE[1:0] MODE - R/W R reserved - - - - - - - - - Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller R/W R/W R R/W R/W R ...

Page 52

... ISP1583; DACK (master) or DIOR (slave): puts data from the ISP1583 on the DMA bus. 10 — DACK (master and slave): strobes data from the DMA bus into the ISP1583 and also puts data from the ISP1583 on the DMA bus. 11 — reserved - ...

Page 53

... Read Polarity: Selects the DIOR strobe polarity. 0 — DIOR is active LOW 1 — DIOR is active HIGH Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller ACK_POL DREQ_ WRITE_ POL POL R/W R/W R/W ISP1583 0 READ_ POL 0 0 R/W © NXP B.V. 2007. All rights reserved 100 ...

Page 54

... LOW HIGH LOW HIGH data (ATA or ATAPI R/W R/W Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller Table 59). ATAPI function data (16-bit) error/feature interrupt reason reserved cylinder low cylinder high drive select status/command alternate status/command reserved DA2 MODE0/DA1 ...

Page 55

... R/W R cylinder low/LBA[15:8] (ATA) or cylinder low (ATAPI R/W R cylinder high/LBA[23:16] (ATA) or cylinder high (ATAPI R/W R/W Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller R/W R/W R R/W R/W R ...

Page 56

... Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller R/W R/W R [1] /command (ATAPI R/W R/W R R/W R/W R/W © NXP B.V. 2007. All rights reserved. ISP1583 100 ...

Page 57

... Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller 11 10 EXT_EOT INT_EOT INTRQ_ PENDING R/W R BSY_ TF_RD_ DONE DONE INTRQ_OK R/W R/W 72. ISP1583 9 8 DMA_ XFER_OK R/W R CMD_ reserved R/W - © NXP B.V. 2007. All rights reserved 100 ...

Page 58

... PENDING R/W R IE_BSY_ IE_TF_ IE_CMD_ DONE RD_DONE INTRQ_OK R/W R/W Table 74 EPIDX[2: R/W R/W ISP1583 Table 73. The bit 9 8 IE_DMA_ XFER_OK R/W R reserved R DMADIR R/W R/W © NXP B.V. 2007. All rights reserved 100 ...

Page 59

... Figure 17). x shows the bit allocation of the 2-byte register. Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller DMA_STROBE_CNT[4: R/W R/W R/W Table 54). The strobe duration cycles 004aaa125 ISP1583 R/W © NXP B.V. 2007. All rights reserved 100 ...

Page 60

... Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller 11 10 BURSTCOUNTER[12: R/W R/W R R/W R/W R/W Table 70 and Table 71 EP7TX - - - - - - R/W ISP1583 R R/W Table 80. 24 EP7RX R/W © NXP B.V. 2007. All rights reserved 100 ...

Page 61

... DMA status: Logic 1 indicates a change in the DMA Interrupt Reason register. HS_STAT High speed status: Logic 1 indicates a change from full-speed to high-speed mode (HS connection). This bit is not set, when the system goes into full-speed suspend. Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller EP4TX EP4RX ...

Page 62

... Chip ID register: bit description Symbol Description CHIPID[15:8] Chip ID: lower byte (15h) CHIPID[7:0] Chip ID: upper byte (82h) VERSION[7:0] Version: version number (30h) Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller …continued Table 82 ...

Page 63

... SFIRL[7: R/W R/W Scratch register: bit description Symbol Description SFIRH[7:0] Scratch firmware information register (higher byte) SFIRL[7:0] Scratch firmware information register (lower byte) Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller SOFR[10: ...

Page 64

... NXP Semiconductors 8.5.5 Unlock Device register (address: 7Ch) To protect registers from getting corrupted when the ISP1583 goes into suspend, the write operation is disabled if bit PWRON in the Mode register is set to logic 0. In this case, when the chip resumes, the Unlock Device command must first be issued to this register before attempting to write to the rest of the registers ...

Page 65

... J-State: Logic 1 sets the DP and DM pins to the J state. SE0_NAK SE0 NAK: Logic 1 sets the DP and DM pins to a high-speed quiescent state. The device only responds to a valid high-speed IN token with a NAK. Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller © NXP B.V. 2007. All rights reserved 100 ...

Page 66

... A LI pins DP, DM AGND BUS and DGND other pins Conditions V = 3.3 V CC(3V3) on pins DP and +85 C; typical values at T amb Conditions full-speed Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller Min Max 0.5 +4.6 0.5 +4.6 [1] 0 0.5 CC(3V3) - 100 4000 +4000 2000 ...

Page 67

... OTG register only when bit DP is set in the OTG register = +85 C; unless otherwise specified. amb Conditions V V I(DP) I(DM) range DI Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller = 25 C; unless otherwise specified. amb Min Typ Max [ 1.65 1.8 1 ...

Page 68

... V < V < 3 pin to GND steady-state drive = +85 C; unless otherwise specified. amb Conditions crystal oscillator running = + pF; R amb L Conditions pF Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller [1] Min Typ Max 0.9 - 1.5 0 0.4 2 ...

Page 69

... Figure 19 Figure 19 accepted as EOP; see Figure 18 rejected as EOP; see Figure 20 crossover point extended differential data to SE0/EOP skew PERIOD DEOP Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller = 1 test circuit of PU TERM Min Typ Max [ 111.11 [1][2] 1 ...

Page 70

... Remark: In the following subsections, RW_N/RD_N, DS_N/WR_N, READY/IORDY and ALE/A0 refer to the ISP1583 pin. 12.1.1 Generic processor mode BUS_CONF/DA0 = HIGH: generic processor mode: 12.1.1.1 8051 mode MODE0/DA1 = HIGH: 8051 mode; see Table 100. ISP1583 register access timing parameters: separate address and data buses CC(I/O) CC(3V3) Symbol ...

Page 71

... READY/IORDY HIGH to RW_N/RD_N or RDY1 DS_N/WR_N HIGH of the last access CS_N A [ 7:0 ] (read) DATA [ 15:0 ] RW_N/RD_N (write) DATA [ 15:0 ] DS_N/WR_N Fig 21. ISP1583 register access timing: separate address and data buses (8051 mode) ISP1583_6 Product data sheet = 3 +85 C. GND amb Conditions T cy(RW) ...

Page 72

... NXP Semiconductors DS_N/WR_N, RW_N/RD_N READY/IORDY Fig 22. ISP1583 ready signal timing 12.1.1.2 Freescale mode MODE0/DA1 = LOW: Freescale mode; see Table 101. ISP1583 register access timing parameters: separate address and data buses CC(I/O) CC(3V3) Symbol Parameter Reading or writing t DS_N/WR_N LOW pulse width WLWH ...

Page 73

... NXP Semiconductors CS_N AD [ 7:0 ] (read) DATA [ 15:0 ] (write) DATA [ 15:0 ] DS_N/WR_N RW_N/RD_N Fig 23. ISP1583 register access timing: separate address and data buses (Freescale mode) DS_N/WR_N READY/IORDY Fig 24. ISP1583 ready signal timing ISP1583_6 Product data sheet T cy(RW) t AVWL t t I1VI2L DVWH t WLWH read write Rev. 06 — 20 August 2007 ...

Page 74

... Fig 25. EOT timing in generic processor mode 12.1.2 Split bus mode 12.1.2.1 ALE function 8051 mode • BUS_CONF/DA0 = LOW: split bus mode • MODE1 = LOW: ALE function – MODE0/DA1 = HIGH: 8051 mode; see Table 102. ISP1583 register access timing parameters: multiplexed address/data bus CC(I/O) CC(3V3) Symbol Parameter Reading t ...

Page 75

... NXP Semiconductors CS_N (read 7:0 ] RW_N/RD_N (write 7:0 ] DS_N/WR_N ALE/A0 Fig 26. ISP1583 register access timing: multiplexed address/data bus (8051 mode) Freescale mode • BUS_CONF/DA0 = LOW: split bus mode • MODE1 = LOW: ALE function – MODE0/DA1 = LOW: Freescale mode; see Table 103. ISP1583 register access timing parameters: multiplexed address/data bus 3.6 V ...

Page 76

... CS_N (read 7:0 ] (write 7 I1VLL DS_N/WR_N RW_N/RD_N ALE/A0 Fig 27. ISP1583 register access timing: multiplexed address/data bus (Freescale mode) 12.1.2.2 A0 function 8051 mode • BUS_CONF/DA0 = LOW: split bus mode • MODE1 = HIGH: A0 function – MODE0/DA1 = HIGH: 8051 mode; see Table 104. ISP1583 register access timing parameters: multiplexed address/data bus 3.6 V ...

Page 77

... RW_N/RD_N t AVWH DS_N/WR_N (write 7:0 ] DS_N/WR_N RW_N/RD_N Fig 28. ISP1583 register access timing: multiplexed address/data bus (A0 function and 8051 mode) Freescale mode • BUS_CONF/DA0 = LOW: split bus mode • MODE1 = HIGH: A0 function – MODE0/DA1 = LOW: Freescale mode; see Table 105. ISP1583 register access timing parameters: multiplexed address/data bus 3.6 V ...

Page 78

... NXP Semiconductors Table 105. ISP1583 register access timing parameters: multiplexed address/data bus CC(I/O) CC(3V3) Symbol Parameter t DS_N/WR_N HIGH to CS_N HIGH delay RHSH t DS_N/WR_N LOW pulse width RLRH t DS_N/WR_N HIGH (address) to DS_N/WR_N WHRH HIGH (data read) delay Writing t ALE/A0 set-up time before DS_N/WR_N LOW ...

Page 79

... A0WL ALE/A0 CS_N (read 7:0 ] RW_N/RD_N t AVWH DS_N/WR_N (write 7:0 ] DS_N/WR_N RW_N/RD_N Fig 29. ISP1583 register access timing: multiplexed address/data bus (A0 function and Freescale mode) (1) Programmable polarity: shown as active LOW. Fig 30. EOT timing in split bus mode ISP1583_6 Product data sheet T cy(RW) t RLDV address data ...

Page 80

... NXP Semiconductors 12.2 DMA timing 12.2.1 PIO mode Remark: In the following subsections, RW_N/RD_N, DS_N/WR_N, READY/IORDY and ALE/A0 refer to the ISP1583 pin. Table 106. PIO mode timing parameters CC(I/O) CC(3V3) Symbol Parameter T read or write cycle time cy1(min) t address to DIOR or DIOW on set-up su1(min) time ...

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... READY/IORDY negated for at least 5 ns after t su4 before READY/IORDY is asserted. d1 Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller su2 su3 h3(min su5 t w3 expires: no wait state is generated. su4 expires: a wait su4 © NXP B.V. 2007. All rights reserved. ISP1583 004aaa921 81 of 100 ...

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... Fig 32. GDMA slave mode timing: DIOR (master) and DIOW (slave) ISP1583_6 Product data sheet = 3 +85 C. GND amb Conditions cy1 t su3 su2 h3 Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller Figure 32 Figure 33 Figure 34 Min Typ Max Unit 33. ...

Page 83

... Product data sheet su3 cy1 su2 cy1 su2 h3 Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller mgt502 mgt501 © NXP B.V. 2007. All rights reserved 100 ...

Page 84

... greater than the sum of t w1(min) T cy1 su2 h2 © NXP B.V. 2007. All rights reserved. ISP1583 Unit cy1 w1 w2 and host w2(min) mgt506 ...

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... ISP1583 ALE/A0 INT RW_N/RD_N address read interrupt latch strobe enable ALE INTn_N RD_N 8051 MICROCONTROLLER Figure 38. Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller ISP1583 8 AD[7:0] ALE/A0 16 DATA[15:0] RW_N/RD_N DS_N/WR_N CS_N 004aaa273 DATA [ 15:0 ] DREQ DACK DMA DIOW DIOR DS_N/WR_N AD[7:0] write address ...

Page 86

... NXP Semiconductors Fig 38. Load impedance for the DP and DM pins (full-speed mode) ISP1583_6 Product data sheet DUT In full-speed mode, an internal 1.5 k pull-up resistor is connected to pin DP. Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller test point mgt495 © NXP B.V. 2007. All rights reserved. ...

Page 87

... JEITA MO-220 - - - Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller detail 4.85 0.5 0.5 7.5 7.5 0.1 4.55 0.3 EUROPEAN PROJECTION ISP1583 SOT804 0.05 0.05 0.1 ISSUE DATE 03-03-26 © NXP B.V. 2007. All rights reserved 100 ...

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... 6.1 6.1 0.5 4.5 4.5 0.15 5.9 5.9 REFERENCES JEDEC JEITA MO-195 - - - Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller detail 0.08 0.05 0.1 EUROPEAN PROJECTION ISP1583 SOT543-1 y ISSUE DATE 00-11-22 02-04-09 © NXP B.V. 2007. All rights reserved 100 ...

Page 89

... 4.1 4.1 0.4 2.8 2.8 0.15 3.9 3.9 REFERENCES JEDEC JEITA - - - - - - Rev. 06 — 20 August 2007 Hi-Speed USB Peripheral Controller detail 0.05 0.08 0.1 EUROPEAN PROJECTION ISP1583 SOT969-1 ISSUE DATE 06-09-22 06-09-27 © NXP B.V. 2007. All rights reserved 100 ...

Page 90

... Solder bath specifications, including temperature and impurities ISP1583_6 Product data sheet Hi-Speed USB Peripheral Controller Rev. 06 — 20 August 2007 ISP1583 © NXP B.V. 2007. All rights reserved 100 ...

Page 91

... Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 42. Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller Figure 42) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...

Page 92

... Generic DMA High-Speed Integrated Development Environment Multi-word DMA Memory Management Unit Magneto-Optical Non-Return-to-Zero Inverted On-The-Go Printed-Circuit Board Personal Digital Assistant Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller peak temperature time 001aac844 © NXP B.V. 2007. All rights reserved 100 ...

Page 93

... Packet IDentifier Parallel Interface Engine Parallel Input/Output Phase-Locked Loop Physical Power-On Reset Single-Ended Zero Serial Interface Engine Session Request Protocol Transistor-Transistor Logic Universal Serial Bus Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller © NXP B.V. 2007. All rights reserved 100 ...

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... NXP Semiconductors 19. Revision history Table 112. Revision history Document ID Release date ISP1583_6 20070820 • Modifications: Added the ISP1583ET1 package. • Figure 1 “Block • Updated • Added Section 7.10 “Reconfiguring endpoints” on page • Figure 7 “Resistor and electrolytic or tantalum capacitor needed for V note. • ...

Page 95

... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. SoftConnect — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 06 — 20 August 2007 ISP1583 Hi-Speed USB Peripheral Controller © NXP B.V. 2007. All rights reserved 100 ...

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... NXP Semiconductors 22. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 3. Bus configuration modes . . . . . . . . . . . . . . . . .17 Table 4. ISP1583 pin status . . . . . . . . . . . . . . . . . . . . . .18 Table 5. ISP1583 output pin status . . . . . . . . . . . . . . . .18 Table 6. Power modes . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 7. Operation truth table for SoftConnect . . . . . . .26 Table 8. Operation truth table for clock off during suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 9 ...

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... Table 102.ISP1583 register access timing parameters: multiplexed address/data bus . . . . . . . . . . . . .74 Table 103.ISP1583 register access timing parameters: multiplexed address/data bus . . . . . . . . . . . . .75 Table 104.ISP1583 register access timing parameters: multiplexed address/data bus . . . . . . . . . . . . .76 Table 105.ISP1583 register access timing parameters: multiplexed address/data bus . . . . . . . . . . . . .77 Table 106.PIO mode timing parameters . . . . . . . . . . . . . .80 Table 107 ...

Page 98

... Fig 9. Oscilloscope reading: with resistor and capacitor in the network . . . . . . . . . . . . . . . . . . . .22 Fig 10. POR timing .23 Fig 11. Clock with respect to the external POR . . . . . . . .23 Fig 12. ISP1583 with a 3.3 V supply . . . . . . . . . . . . . . . .24 Fig 13. Power-sharing mode . . . . . . . . . . . . . . . . . . . . . .25 Fig 14. Interrupt pin status during power off in power-sharing mode . . . . . . . . . . . . . . . . . . . . . .25 Fig 15. Self-powered mode . . . . . . . . . . . . . . . . . . . . . . .27 Fig 16. Bus-powered mode . . . . . . . . . . . . . . . . . . . . . . .28 Fig 17 ...

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... Split bus mode . . . . . . . . . . . . . . . . . . . . . . . . 74 12.1.2.1 ALE function 12.1.2.2 A0 function . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.2 DMA timing 12.2.1 PIO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.2.2 GDMA slave mode . . . . . . . . . . . . . . . . . . . . . 82 12.2.3 MDMA mode . . . . . . . . . . . . . . . . . . . . . . . . . 84 13 Application information . . . . . . . . . . . . . . . . . 85 14 Test information Package outline . . . . . . . . . . . . . . . . . . . . . . . . 87 16 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Rev. 06 — 20 August 2007 ISP1583 continued >> © NXP B.V. 2007. All rights reserved 100 ...

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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ISP1583 All rights reserved. Date of release: 20 August 2007 Document identifier: ISP1583_6 ...

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