ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 21

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 17.
Table 18.
ISP1561_2
Product data sheet
Bit
31 to 0
Bit
15 to 0
Symbol
BAR0[31:0]
Symbol
SVID[15:0]
BAR0 register: bit description
Subsystem Vendor ID register: bit description
8.2.1.10 BIST register (address: 0Fh)
8.2.1.11 Base Address registers
8.2.1.12 CardBus CIS Pointer register (address: 28h)
8.2.1.13 Subsystem Vendor ID register (address: 2Ch)
This register is used for control and status of Built In Self Test (BIST). Devices that do not
support BIST must always return logic 0, that is, treat it as a reserved register. A device
whose BIST is invoked must not prevent normal operation of the PCI bus. The BIST
register is not used in the ISP1561. Therefore, the logic value returned is always zero.
Power-up software must build a consistent address map before booting the machine to an
operating system. This means it must determine how much memory is in the system, and
how much address space the I/O controllers in the system require. After determining this
information, power-up software can map the I/O controllers into reasonable locations and
proceed with system boot. To do this mapping in a device-independent manner, base
registers for this mapping are placed in the predefined header portion of configuration
space.
Bit 0 in all Base Address registers is read-only and used to determine whether the register
maps into memory or I/O space. Base Address registers that map to memory space must
return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in
bit 0.
The bit description of the BAR0 register is given in
Base Address register 0 (BAR0) — (address: 10h)
Base Address register 1, 2, 3, 4, 5 (BAR1, 2, 3, 4, 5) — (address: 14h, 18h, 1Ch, 20h
and 24h): The BAR1, 2, 3, 4, 5 register spaces are not used in the ISP1561.
This 4-byte register is used by devices that want to share silicon between CardBus and
PCI. The CardBus CIS Pointer register is used to point to the Card Information Structure
(CIS) for the CardBus card. This register is not implemented in the ISP1561.
The Subsystem Vendor ID register is used to uniquely identify the expansion board or
subsystem where the PCI device resides. This register allows expansion board vendors to
distinguish their boards, even though the boards may have the same vendor ID and device
ID.
Subsystem vendor IDs are assigned by PCI-SIG to maintain uniqueness. The bit
description of the Subsystem Vendor ID register is given in
Access
R/W
Access
R
Value
1131h
Value
0000 0000h
Description
Subsystem Vendor ID: 1131h is the subsystem vendor ID assigned to NXP
Semiconductors.
Rev. 02 — 5 March 2007
Description
Base Address to Memory-Mapped Host Controller Register
Space: The memory size required by OHCI and EHCI are 4 kB and
256 bytes, respectively. Therefore, BAR0[31:12] is assigned to the two
OHCI ports, and BAR0[31:8] is assigned to the EHCI port.
Table
17.
Table
HS USB PCI Host Controller
18.
© NXP B.V. 2007. All rights reserved.
ISP1561
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