ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 25

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 30.
Table 32.
ISP1561_2
Product data sheet
Bit
15 to 0
Bit
7 to 0
Symbol
PORTWAKE
CAP[15:0]
Symbol
CAP_ID[7:0]
PORTWAKECAP register: bit description
CAP_ID register: bit description
8.2.2.3 PORTWAKECAP register (address: 62h)
8.2.3.1 CAP_ID register (address: value read from address 34h + 0h)
8.2.3 Power management registers
Table 29.
The PORTWAKECAP register is a 2-byte register, and the bit description is given in
Table
Bit positions 1 to 15 in the mask correspond to a physical port implemented on the current
EHCI controller. Logic 1 in a bit position indicates that a device connected below the port
can be enabled as a wake-up device and the port may be enabled for disconnect or
connect, or overcurrent events as wake-up events. This is an information only mask
register. The bits in this register do not affect the actual operation of the EHCI Host
Controller. The system-specific policy can be established by BIOS initializing this register
to a system-specific value. The system software uses the information in this register when
enabling devices and ports for remote wake-up.
Table 31.
The Capability Identifier (CAP_ID) register when read by the system software as 01h
indicates that the data structure currently being pointed to is the PCI power management
data structure. Each function of a PCI device may have only one item in its capability list
with CAP_ID set to 01h. The bit description of the register is given in
FLADJ value
:
31(1Fh)
32 (20h)
:
62 (3Eh)
63 (3Fh)
Offset
value read from address 34h + 0h
value read from address 34h + 1h
value read from address 34h + 2h
value read from address 34h + 4h
value read from address 34h + 6h
value read from address 34h + 7h
Access
R
Access
R/W
30. This register is used to establish a policy about which ports are for wake events.
FLADJ value as a function of SOF cycle time
Power management registers
Value
01h
Value
001Fh
Description
ID: This field when 01h identifies the linked list item as being PCI power
management registers.
Description
Port Wake Up Capability Mask: EHCI does not implement this feature.
Rev. 02 — 5 March 2007
Register
Capability Identifier (CAP_ID)
Next Item Pointer (NEXT_ITEM_PTR)
Power Management Capabilities (PMC)
Power Management Control/Status (PMCSR)
Power Management Control/Status PCI-to-PCI Bridge
Support Extensions (PMCSR_BSE)
Data
SOF cycle time (480 MHz)
:
59984
60000
:
60480
60496
…continued
HS USB PCI Host Controller
Table
© NXP B.V. 2007. All rights reserved.
ISP1561
32.
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