ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 28

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 36.
[1]
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Sticky bit, if the function supports PME# from D3
function does not support PME# from D3
PMCSR register: bit allocation
PMES
R/W
X
15
7
0
-
[1]
Table 37.
Bit
15
14 to 13
12 to 9
8
7 to 2
14
R
0
6
0
-
PMCSR register: bit description
DS[1:0]
Symbol
PMES
DS[1:0]
D_S[3:0]
PMEE
-
cold
.
13
R
0
5
0
cold
-
, then X is indeterminate at the time of initial operating system boot; X is 0 if the
reserved
Rev. 02 — 5 March 2007
Description
PME Status: This bit is set when the function normally asserts the
PME# signal independent of the state of the PME_EN bit. Writing
logic 1 to this bit clears it and causes the function to stop asserting
PME#, if enabled. Writing logic 0 has no effect. This bit defaults to
logic 0, if the function does not support the PME# generation from
D3
this bit is sticky and must be explicitly cleared by the operating system
each time the operating system is initially loaded.
Data Scale: This two-bit read-only field indicates the scaling factor
when interpreting the value of the Data register. The value and
meaning of this field vary, depending on which data value is selected by
the D_S field. This field is a required component of the Data register
(offset 7) and must be implemented, if the Data register is
implemented. If the Data register is not implemented, this field must
return 00b when PMCSR is read.
Data Select: This four-bit field selects the data that is reported through
the Data register and the D_S field. This field is a required component
of the Data register (offset 7) and must be implemented if the Data
register is implemented. If the Data register is not implemented, this
field must return 00b when PMCSR is read.
PME Enabled: Logic 1 allows the function to assert PME#. When it is
logic 0, PME# assertion is disabled. This bit defaults to logic 0 if the
function does not support the PME# generation from D3
function supports PME# from D3
explicitly be cleared by the operating system each time the operating
system is initially loaded. Functions that do not support the PME#
generation from any D-state (that is, PMC[15:11] = 0 0000b), may
hardwire this bit to be read-only always returning logic 0 when read by
system software.
reserved
cold
. If the function supports the PME# generation from D3
R/W
12
0
4
0
-
R/W
11
0
3
0
-
D_S[3:0]
cold
R/W
, then this bit is sticky and must
10
0
2
0
-
HS USB PCI Host Controller
R/W
R/W
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1561
PS[1:0]
cold
. If the
cold
PMEE
R/W
R/W
X
27 of 103
, then
8
0
0
[1]