ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 64

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 91.
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
HceInput register: bit allocation
11.2.2 HceInput register (address: content of the base address register + 104h)
31
0
-
Table 90.
The HceInput register is a 4-byte register, and the bit allocation is given in
I/O data that is written to ports 60h and 64h is captured in this register, when emulation is
enabled. This register may directly be read or written by accessing it in the Host
Controller’s operational register space. When directly accessed in a memory cycle, reads
and writes of this register have no side effects.
Bit
31 to 9
8
7
6
5
4
3
2
1
0
30
0
-
Symbol
-
A20S
IRQ12A
IRQ1A
GA20S
EIRQEN
IRQEN
C_P
EI
EE
HceControl register: bit description
29
0
-
Description
reserved
A20 State: This bit indicates the current state of gate A20 on the keyboard
controller. It is used to compare against value written to 60h when GA20S
(Gate A20 Sequence) is active.
IRQ12 Active: This bit indicates that a positive transition on IRQ12 from
the keyboard controller has occurred. Writing logic 1 sets IRQ12 to logic 0
(inactive). Writing logic 0 to this bit has no effect.
IRQ1 Active: This bit indicates that a positive transition on IRQ1 from the
keyboard controller has occurred. Writing logic 1 sets IRQ1 to logic 0
(inactive). Writing logic 0 to this bit has no effect.
Gate A20 Sequence: This bit is set by the Host Controller when a data
value of D1h is written to I/O port 64h and cleared, on a write to I/O port
64h of any value other than D1h.
External IRQ Enable: When this bit is set to logic 1, IRQ1 and IRQ12 from
the keyboard controller cause an emulation interrupt. This bit is
independent of the setting of the EE (Emulation Enable) bit in this register.
IRQ Enable: When this bit is set, the Host Controller generates IRQ1 or
IRQ12 as long as the OUT_FULL (Output Full) bit in HceStatus is set to
logic 1. If the AUX_OUT_FULL (Auxiliary Output Full) bit of HceStatus is
logic 0, then IRQ1 is generated; if it is logic 1, then an IRQ12 is generated.
Character Pending: When this bit is set, an emulation interrupt is
generated when the OUT_FULL (Output Full) bit of the HceStatus register
is set to logic 0.
Emulation Interrupt: This bit shows the emulation interrupt condition.
0 — Legacy emulation enabled
1 — Legacy emulation disabled
Emulation Enable: When this bit is set to logic 1, the Host Controller is
enabled for legacy emulation. The Host Controller decodes accesses to
I/O registers 60h and 64h, and enables interrupts on IRQ1 or IRQ12, or
both. The Host Controller also generates an emulation interrupt at
appropriate times to invoke the emulation software.
Rev. 02 — 5 March 2007
28
0
-
reserved
27
0
-
26
0
-
HS USB PCI Host Controller
25
0
-
© NXP B.V. 2007. All rights reserved.
ISP1561
Table
91. The
63 of 103
24
0
-