ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 23

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 22.
Table 23.
[1]
Table 24.
[1]
ISP1561_2
Product data sheet
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
X is 01h for OHCI1 and OHCI2; X is 02h for EHCI.
X is 2Ah for OHCI1 and OHCI2; X is 10h for EHCI.
Symbol
IP[7:0]
Symbol
MIN_GNT[7:0] R
Symbol
MAX_LAT[7:0]
Interrupt Pin register: bit description
MIN_GNT register: bit description
MAX_LAT register: but description
8.2.1.18 Interrupt Pin register (address: 3Dh)
8.2.1.19 MIN_GNT and MAX_LAT registers (address: 3Eh and 3Fh)
8.2.1.20 TRDY Timeout register (R/W: 40h)
8.2.1.21 Retry Timeout register (R/W: 41h)
This 1-byte register is use to specify which interrupt pin the device or device function uses.
The bit description is given in
Devices or functions that do not use an interrupt pin must put a logic 0 in this register.
The Minimum Grant (MIN_GNT) and Maximum Latency (MAX_LAT) registers are used to
specify the desired settings of the device for latency timer values. For both registers, the
value specifies a period of time in units of 250 ns. Values of 0 indicates that the device has
no major requirements for the settings of latency timers.The MIN_GNT register bit
description is given in
The default and recommended value is 00h, TRDY time-out disabled. This value can,
however, be modified. It is an implementation-specific register, and not a standard PCI
configuration register.
The TRDY timer is 13 bits: the lower 5 bits are fixed as logic 0 and the upper 8 bits are
determined by the TRDY time-out register value. The time-out is calculated by multiplying
the 13-bit timer with the PCICLK cycle time.
This register determines the delay for the UE bit setting if a target does not assert its
TDRY signal.
The default value is 80h. This value can, however, be modified. Programming this register
as 00h means that retry time-out is disabled. This is an implementation-specific register,
and not a standard PCI configuration register.
The time-out is determined by multiplying the register value with the PCICLK cycle time.
This register determines the delay to set the UE bit if a RETRY time-out occurs.
Access
R/W
The MAX_LAT register bit description is given in
Access
Access
R
Value
01h
Value
X
Value
X
[1]
[1]
Table
Description
MIN_GNT: It is used to specify how long a burst period the device needs,
assuming a clock rate of 33 MHz.
Description
MAX_LAT: It is used to specify how often the device needs to gain
access to the PCI bus.
Description
Interrupt Pin: INTA# is the default interrupt pin used by the ISP1561.
Rev. 02 — 5 March 2007
23.
Table
22.
Table
24.
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1561
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