ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 16

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 6.
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Command register: bit allocation
8.2.1.3 Command register (address: 04h)
SCTRL
15
R
0
7
0
-
This is a 2-byte register that provides coarse control over the ability of a device to
generate and respond to PCI cycles. The bit allocation of the Command register is given
in
the PCI bus for all accesses, except configuration accesses. All devices are required to
support this base level of functionality. Individual bits in the Command register may or may
not support this base level of functionality.
Table 7.
Bit
15 to 10
9
8
7
6
Table
PER
R/W
14
0
6
0
-
6. When logic 0 is written to this register, the device is logically disconnected from
Command register: bit description
Symbol
-
FBBE
SERRE
SCTRL
PER
VGAPS
13
R
0
5
0
-
reserved
Rev. 02 — 5 March 2007
Description
reserved
Fast Back-to-Back Enable: This bit controls whether a master can do
fast back-to-back transactions to various devices. The initialization
software must set this bit if all targets are fast back-to-back capable.
0 — Fast back-to-back transactions are only allowed to the same
agent (value after RST#).
1 — The master is allowed to generate fast back-to-back transactions
to different agents.
SERR# Enable: This bit is an enable bit for the SERR# driver. All
devices that have an SERR# pin must implement this bit. Address
parity errors are reported only if this bit and the PER bit are logic 1.
0 — Disable the SERR# driver.
1 — Enable the SERR# driver.
Stepping Control: This bit controls whether a device does address
and data stepping. Devices that never do stepping must clear this bit.
Devices that always do stepping must set this bit. Devices that can do
either, must make this bit read/write and initialize it to logic 1 after
RST#.
Parity Error Response: This bit controls the response of a device to
parity errors. When the bit is set, the device must take its normal
action when a parity error is detected. When the bit is logic 0, the
device sets its Detected Parity Error status bit (bit 15 in the Status
register) when an error is detected, but does not assert PERR# and
continues normal operation. The state of this bit after RST# is logic 0.
Devices that check parity must implement this bit. Devices are
required to generate parity, even if parity checking is disabled.
MWIE
R/W
12
0
4
0
-
SC
11
R
0
3
0
-
R/W
BM
10
0
2
0
-
HS USB PCI Host Controller
FBBE
R/W
R/W
MS
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1561
SERRE
R/W
R/W
IOS
15 of 103
8
0
0
0