ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 75

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 107. USBINTR register: bit allocation
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
11.4.3 USBINTR register (address: content of the base address register + 14h)
31
23
15
0
0
0
7
0
-
-
-
-
reserved
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the
corresponding interrupt to the software. When a bit is set and the corresponding interrupt
is active, an interrupt is generated to the host. Interrupt sources that are disabled in this
register still appear in the USBSTS to allow the software to poll for events. The USBSTS
register bit allocation is give in
Table 108. USBINTR register: bit description
Bit
31 to 6
5
4
3
30
22
14
0
0
0
6
0
-
-
-
-
Symbol
-
IAAE
HSEE
FLRE
IAAE
R/W
29
21
13
0
0
0
5
0
-
-
-
Rev. 02 — 5 March 2007
Description
reserved
Interrupt on Asynchronous Advance Enable: When this bit and the
IAA (Interrupt on Asynchronous Advance) bit in the USBSTS register
are set, the Host Controller issues an interrupt at the next interrupt
threshold. The interrupt is acknowledged by software clearing bit IAA.
Host System Error Enable: When this bit and the Host System Error
Status bit in the USBSTS register are set, the Host Controller issues
an interrupt. The interrupt is acknowledged by software clearing the
HSE (Host System Error) bit.
Frame List Rollover Enable: When this bit and the FLR (Frame List
Rollover) bit in the USBSTS register are set, the Host Controller
issues an interrupt. The interrupt is acknowledged by software
clearing the FLR (Frame List Rollover) bit.
HSEE
Table
R/W
28
20
12
0
0
0
4
0
-
-
-
reserved
reserved
reserved
107.
FLRE
R/W
27
19
11
0
0
0
3
0
-
-
-
PCIE
R/W
26
18
10
0
0
0
2
0
-
-
-
HS USB PCI Host Controller
USBERR
INTE
R/W
25
17
0
0
9
0
1
0
-
-
-
© NXP B.V. 2007. All rights reserved.
ISP1561
USBINTE
R/W
74 of 103
24
16
0
0
8
0
0
0
-
-
-