ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 100

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Revision ID register: bit description . . . . . . . . .18
Table 11. Class Code register: bit allocation . . . . . . . . . .18
Table 12. Class Code register: bit description . . . . . . . . .18
Table 13. CacheLine Size register: bit description . . . . .19
Table 14. Latency Timer register: bit description . . . . . . .19
Table 15. Header Type register: bit allocation . . . . . . . . .19
Table 16. Header Type register: bit description . . . . . . . .19
Table 17. BAR0 register: bit description . . . . . . . . . . . . .20
Table 18. Subsystem Vendor ID register: bit description .20
Table 19. Subsystem ID register: bit description . . . . . . .21
Table 20. Capabilities Pointer register: bit description . . .21
Table 21. Interrupt Line register: bit description . . . . . . .21
Table 22. Interrupt Pin register: bit description . . . . . . . .22
Table 23. MIN_GNT register: bit description . . . . . . . . . .22
Table 24. MAX_LAT register: but description . . . . . . . . .22
Table 25. EHCI-specific PCI registers . . . . . . . . . . . . . . .23
Table 26. SBRN register: bit description . . . . . . . . . . . . .23
Table 27. FLADJ register: bit allocation . . . . . . . . . . . . . .23
Table 28. FLADJ register: bit description . . . . . . . . . . . .23
Table 29. FLADJ value as a function of SOF cycle time .23
Table 30. PORTWAKECAP register: bit description . . . .24
Table 31. Power management registers . . . . . . . . . . . . .24
Table 32. CAP_ID register: bit description . . . . . . . . . . .24
Table 33. NEXT_ITEM_PTR register: bit description . . .25
Table 34. PMC register: bit allocation . . . . . . . . . . . . . . .25
Table 35. PMC register: bit description . . . . . . . . . . . . . .25
Table 36. PMCSR register: bit allocation . . . . . . . . . . . . .27
Table 37. PMCSR register: bit description . . . . . . . . . . .27
Table 38. PMCSR_BSE register: bit allocation . . . . . . . .28
Table 39. PMCSR_BSE register: bit description . . . . . . .28
Table 40. PCI bus power and clock control . . . . . . . . . . .29
Table 41. Data register: bit description . . . . . . . . . . . . . .29
Table 42. USB Host Controller registers . . . . . . . . . . . . .33
Table 43. HcRevision register: bit allocation . . . . . . . . . .35
Table 44. HcRevision register: bit description . . . . . . . . .36
Table 45. HcControl register: bit allocation . . . . . . . . . . .36
Table 46. HcControl register: bit description . . . . . . . . . .37
Table 47. HcCommandStatus register: bit allocation . . .39
ISP1561_2
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
PCI configuration space registers of OHCI1,
OHCI2 and EHCI . . . . . . . . . . . . . . . . . . . . . . .13
Vendor ID register: bit description . . . . . . . . . .14
Device ID register: bit description . . . . . . . . . .14
Command register: bit allocation . . . . . . . . . . .15
Command register: bit description . . . . . . . . . .15
Status register: bit allocation . . . . . . . . . . . . . .16
Status register: bit description . . . . . . . . . . . . .17
Rev. 02 — 5 March 2007
Table 48. HcCommandStatus register: bit description . . 39
Table 49. HcInterruptStatus register: bit allocation . . . . . 40
Table 50. HcInterruptStatus register: bit description . . . . 41
Table 51. HcInterruptEnable register: bit allocation . . . . 42
Table 52. HcInterruptEnable register: bit description . . . 42
Table 53. HcInterruptDisable register: bit allocation . . . . 43
Table 54. HcInterruptDisable register: bit description . . . 44
Table 55. HcHCCA register: bit allocation . . . . . . . . . . . . 45
Table 56. HcHCCA register: bit description . . . . . . . . . . 45
Table 57. HcPeriodCurrentED register: bit allocation . . . 45
Table 58. HcPeriodCurrentED register: bit description . . 46
Table 59. HcControlHeadED register: bit allocation . . . . 46
Table 60. HcControlHeadED register: bit description . . . 46
Table 61. HcControlCurrentED register: bit allocation . . 47
Table 62. HcControlCurrentED register: bit description . 47
Table 63. HcBulkHeadED register: bit allocation . . . . . . 47
Table 64. HcBulkHeadED register: bit description . . . . . 48
Table 65. HcBulkCurrentED register: bit allocation . . . . . 48
Table 66. HcBulkCurrentED register: bit description . . . 49
Table 67. HcDoneHead register: bit allocation . . . . . . . . 49
Table 68. HcDoneHead register: bit description . . . . . . . 49
Table 69. HcFmInterval register: bit allocation . . . . . . . . 50
Table 70. HcFmInterval register: bit description . . . . . . . 50
Table 71. HcFmRemaining register: bit allocation . . . . . 51
Table 72. HcFmRemaining register: bit description . . . . 51
Table 73. HcFmNumber register: bit allocation . . . . . . . . 51
Table 74. HcFmNumber register: bit description . . . . . . 52
Table 75. HcPeriodicStart register: bit allocation . . . . . . 52
Table 76. HcPeriodicStart register: bit description . . . . . 53
Table 77. HcLSThreshold register: bit allocation . . . . . . 53
Table 78. HcLSThreshold register: bit description . . . . . 54
Table 79. HcRhDescriptorA register: bit allocation . . . . . 54
Table 80. HcRhDescriptorA register: bit description . . . . 55
Table 81. HcRhDescriptorB register: bit allocation . . . . . 56
Table 82. HcRhDescriptorB register: bit description . . . . 56
Table 83. HcRhStatus register: bit allocation . . . . . . . . . 57
Table 84. HcRhStatus register: bit description . . . . . . . . 57
Table 85. HcRhPortStatus[1:4] register: bit allocation . . 58
Table 86. HCRhPortStatus[1:4] register: bit description . 59
Table 87. Legacy support registers . . . . . . . . . . . . . . . . . 62
Table 88. Emulated registers . . . . . . . . . . . . . . . . . . . . . 62
Table 89. HceControl register: bit allocation . . . . . . . . . . 62
Table 90. HceControl register: bit description . . . . . . . . . 63
Table 91. HceInput register: bit allocation . . . . . . . . . . . . 63
Table 92. HceInput register: bit description . . . . . . . . . . 64
Table 93. HceOutput register: bit allocation . . . . . . . . . . 64
Table 94. HceOutput register: bit description . . . . . . . . . 65
Table 95. HceStatus register: bit allocation . . . . . . . . . . . 65
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1561
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