ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 76

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 109. FRINDEX register: bit allocation
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
11.4.4 FRINDEX register (address: content of the base address register + 18h)
R/W
31
23
15
0
0
0
7
0
-
-
-
reserved
Table 108. USBINTR register: bit description
The Frame Index (FRINDEX) register is used by the Host Controller to index into the
periodic frame list. The register updates every 125 s, once each microframe. Bits N to 3
are used to select a particular entry in the periodic frame list during periodic schedule
execution. The number of bits used for the index depends on the size of the frame list as
set by system software in the FLS (Frame List Size) field in the USBCMD register. This
register must be written as a DWORD. Byte writes produce undefined results. This
register cannot be written unless the Host Controller is in the halted state, as indicated by
the HCH (HC Halted) bit. A write to this register while the RS (Run/Stop) bit is set
produces undefined results. Writes to this register also affect the SOF value. The bit
allocation is given in
Bit
2
1
0
R/W
30
22
14
0
0
0
6
0
-
-
-
Symbol
PCIE
USB
ERRINTE
USBINTE
R/W
R/W
29
21
13
0
0
0
5
0
-
-
Table
Rev. 02 — 5 March 2007
Description
Port Change Interrupt Enable: When this bit and the PCD (Port
Change Detect) bit in the USBSTS register are set, the Host Controller
issues an interrupt. The interrupt is acknowledged by software
clearing the PCD (Port Change Detect) bit.
USB Error Interrupt Enable: When this bit and the USBERRINT bit in
the USBSTS register are set, the Host Controller issues an interrupt at
the next interrupt threshold. The interrupt is acknowledged by software
clearing the USBERRINT bit.
USB Interrupt Enable: When this bit and the USBINT bit in the
USBSTS register are set, the Host Controller issues an interrupt at the
next interrupt threshold. The interrupt is acknowledged by software
clearing the USBINT bit.
109.
R/W
R/W
28
20
12
0
0
0
4
0
-
-
FRINDEX[7:0]
reserved
reserved
…continued
R/W
R/W
27
19
11
FRINDEX[13:8]
0
0
0
3
0
-
-
R/W
R/W
26
18
10
0
0
0
2
0
-
-
HS USB PCI Host Controller
R/W
R/W
25
17
0
0
9
0
1
0
-
-
© NXP B.V. 2007. All rights reserved.
ISP1561
R/W
R/W
75 of 103
24
16
0
0
8
0
0
0
-
-