ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 62

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
ISP1561_2
Product data sheet
11.2 USB legacy support registers
Table 86.
The ISP1561 supports legacy keyboard and mouse. Four operational registers are used
to provide the legacy support. Each of these registers is located on a 32-bit boundary. The
offset of these registers is relative to the base address of the Host Controller operational
registers with HceControl located at offset 100h.
Bit
2
1
0
Symbol Description
PSS
PES
CCS
HCRhPortStatus[1:4] register: bit description
On read Port Suspend Status: This bit indicates whether the port is
suspended or is in the resume sequence. It is set by a Set Suspend State
write and cleared when PSSC (Port Suspend Status Change) is set at the
end of the resume interval. This bit is not set if CCS (Current Connect Status)
is cleared. This bit is also cleared when PRSC (Port Reset Status Change) is
set at the end of the port reset or when the Host Controller is placed in the
USBRESUME state. If an upstream resume is in progress, it will propagate to
the Host Controller.
0 — Port is not suspended
1 — Port is suspended
On write Set Port Suspend: The HCD can set the PSS (Port Suspend
Status) bit by writing logic 1 to this bit. Writing logic 0 has no effect. If CCS is
cleared, this write does not set PSS; instead it sets CSS. This informs the
driver that it attempted to suspend a disconnected port.
On read Port Enable Status: This bit indicates whether the port is enabled
or disabled. The root hub may clear this bit when an overcurrent condition,
disconnect event, switched-off power or operational bus error is detected.
This change also causes Port Enabled Status Change to be set. The HCD
can set this bit by writing Set Port Enable and clear it by writing Clear Port
Enable. This bit cannot be set when CCS (Current Connect Status) is
cleared. This bit is also set on completing a port reset when Reset Status
Change is set or on completing a port suspend when Suspend Status
Change is set.
0 — Port is disabled
1 — Port is enabled
On write Set Port Enable: The HCD can set PES (Port Enable Status) by
writing logic 1. Writing logic 0 has no effect. If CCS is cleared, this write does
not set PES, but instead sets CSC (Connect Status Change). This informs
the driver that it attempted to enable a disconnected port.
On read Current Connect Status: This bit reflects the current state of the
downstream port.
0 — No device connected
1 — Device connected
On write Clear Port Enable: The HCD can write logic 1 to this bit to clear the
PES (Port Enable Status) bit. Writing logic 0 has no effect. The CCS (Current
Connect Status) bit, on read, is not affected by any write to Clear Port
Enable.
Remark: This bit always reads logic 1 when the attached device is
nonremovable (DeviceRemoveable[NDP]).
Rev. 02 — 5 March 2007
…continued
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1561
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