ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 66

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 95.
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HceStatus register: bit allocation
11.2.4 HceStatus register (address: content of the base address register + 10Ch)
PARITY
R/W
31
23
15
0
0
0
7
0
-
-
-
Table 94.
The contents of the HceStatus register are returned on an I/O read of port 64h when
emulation is enabled. Reads and writes of port 60h, and writes to port 64h can cause
changes in this register. Emulation software can directly access this register through its
memory address in the Host Controller’s operational register space. Accessing this
register through its memory address produces no side effects.
allocation.
Table 96.
Bit
31 to 8
7 to 0
Bit
31 to 8 -
7
6
5
4
3
TIMEOUT
R/W
30
22
14
0
0
0
6
0
-
-
-
Symbol
PARITY
TIMEOUT
AUX_OUT_
FULL
INH_SW
CMD_DATA
Symbol
-
OUT_DATA[7:0] Output Data: This register holds the data that is returned when an I/O
HceOutput register: bit description
HceStatus register: bit description
AUX_OUT
_FULL
R/W
29
21
13
0
0
0
5
0
-
-
-
Description
reserved
Parity: This bit indicates parity error on keyboard and mouse data.
Time-out: This bit indicates a time-out.
Auxiliary Output Full: IRQ12 is asserted whenever this bit is set to
logic 1, OUT_FULL (Output Full) is set to logic 1, and the IRQEN bit is set.
Inhibit Switch: This bit reflects the state of the keyboard inhibit switch. If
set, the keyboard is active.
Cmd Data: The Host Controller sets this bit to logic 0 on an I/O write to
port 60h and to logic 1 on an I/O write to port 64h.
Rev. 02 — 5 March 2007
Description
reserved
read of port 60h is requested by application software.
INH_SW
R/W
28
20
12
0
0
0
4
0
-
-
-
reserved
reserved
reserved
CMD_DATA
R/W
27
19
11
0
0
0
3
0
-
-
-
FLAG
R/W
26
18
10
0
0
0
2
0
-
-
-
HS USB PCI Host Controller
Table 95
IN_FULL
R/W
25
17
0
0
9
0
1
0
-
-
-
© NXP B.V. 2007. All rights reserved.
contains the bit
ISP1561
OUT_FULL
R/W
65 of 103
24
16
0
0
8
0
0
0
-
-
-