ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 83

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
ISP1561_2
Product data sheet
Table 119. PORTSC 1, 2, 3, 4 register: bit description
[1]
Bit
6
5
4
3
2
1
0
These fields read logic 0, if the Port Power (PP) (bit 12 in register PORTSC 1,2,3,4) is logic 0.
Symbol
FPR
OCC
OCA
PEDC
PED
ECSC
ECCS
Description
Force Port Resume: Logic 1 means resume detected or driven on the port.
Logic 0 means no resume (K-state) detected or driven on the port. Default =
0. Software sets this bit to drive the resume signaling. The Host Controller
sets this bit if a J-to-K transition is detected while the port is in the suspend
state. When this bit changes to logic 1 because a J-to-K transition is
detected, the PCD (Port Change Detect) bit in the USBSTS register is also
set to logic 1. If software sets this bit to logic 1, the Host Controller must not
set the PCD (Port Change Detect) bit. When the EHCI controller owns the
port, the resume sequence follows the sequence specified in
“Universal Serial Bus
driven on the port as long as this bit remains set. Software must time the
resume and clear this bit after the correct amount of time has elapsed.
Clearing this bit causes the port to return to high-speed mode, forcing the
bus below the port into a high-speed idle. This bit will remain at logic 1, until
the port has switched to the high-speed idle. The Host Controller must
complete this transition within 2 ms of software clearing this bit.
Overcurrent Change: Default = 0. This bit is set to logic 1 when there is a
change in overcurrent active. Software clears this bit by setting this bit to
logic 1.
Overcurrent Active: Default = 0. If set to logic 1, this port has an
overcurrent condition. If set to logic 0, this port does not have an overcurrent
condition. This bit will automatically change from logic 1 to logic 0 when the
overcurrent condition is removed.
Port Enable/Disable Change: Logic 1 means the port enabled/disabled
status has changed. Logic 0 means no change. Default = 0. For the root
hub, this bit gets set only when a port is disabled because of appropriate
conditions existing at the EOF2 point. For definition of port error, refer to
Chapter 11 of
this bit by setting it.
Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable.
Default = 0. Ports can only be enabled by the Host Controller as a part of the
reset and enable sequence. Software cannot enable a port by writing logic 1
to this field. The Host Controller will only set this bit when the reset
sequence determines that the attached device is a high-speed device. Ports
can be disabled by either a fault condition or by host software. The bit status
does not change until the port state has actually changed. There may be a
delay in disabling or enabling a port because of other Host Controller and
bus events. When the port is disabled, downstream propagation of data is
blocked on this port, except for reset.
Connect Status Change: Logic 1 means change in ECCS (Current
Connect Status). Logic 0 means no change. Default = 0. This bit indicates a
change has occurred in the port’s ECCS (Current Connect Status). The
Host Controller sets this bit for all changes to the port device connect status,
even if system software has not cleared an existing connect status change.
For example, the insertion status changes twice before system software has
cleared the changed condition, hub hardware will be “setting” an already-set
bit, that is, the bit will remain set. Software clears this bit setting it.
Current Connect Status: Logic 1 indicates a device is present on port.
Logic 0 indicates no device is present. Default = 0. This value reflects the
current state of the port and may not correspond directly to the event that
caused the ECSC (Connect Status Change) bit to be set.
Rev. 02 — 5 March 2007
Ref. 8 “Universal Serial Bus
[1]
Specification”. The resume signaling (full-speed ‘K’) is
…continued
[1]
Specification”. Software clears
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
[1]
ISP1561
Ref. 8
[1]
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