ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 17

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 8.
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Status register: bit allocation
8.2.1.4 Status register (address: 06h)
FBBC
DPE
15
R
R
0
7
0
Table 7.
The Status register is a 2-byte read-only register used to record status information on PCI
bus-related events (bit allocation: see
Bit
5
4
3
2
1
0
reserved
SSE
14
R
0
6
0
-
Command register: bit description
Symbol
VGAPS
MWIE
SC
BM
MS
IOS
66MC
RMA
13
R
R
0
5
0
Rev. 02 — 5 March 2007
Description
VGA Palette Snoop: This bit controls how VGA compatible and
graphics devices handle accesses to VGA palette registers. When this
bit is logic 1, palette snooping is enabled (that is, the device does not
respond to palette register writes and snoops data). When the bit is
logic 0, the device must treat palette write accesses like all other
accesses. VGA compatible devices should implement this bit.
Memory Write and Invalidate Enable: This is an enable bit for using
the Memory Write and Invalidate command. When this bit is logic 1,
masters may generate the command. When it is logic 0, Memory
Writes must be used instead. State after RST# is logic 0. This bit must
be implemented by master devices that can generate the Memory
Write and Invalidate command.
Special Cycles: Controls the action of a device on special cycle
operations. A value of logic 0 causes the device to ignore all special
cycle operations. A value of logic 1 allows the device to monitor
special cycle operations. State after RST# is logic 0.
Bus Master: Controls the ability of a device to act as a master on the
PCI bus. A value of logic 0 disables the device from generating PCI
accesses. A value of logic 1 allows the device to behave as a bus
master. State after RST# is logic 0.
Memory Space: Controls the response of a device to memory space
accesses. A value of logic 0 disables the device response. A value of
logic 1 allows the device to respond to memory space accesses. State
after RST# is logic 0.
IO Space: Controls the response of a device to I/O space accesses. A
value of logic 0 disables the device response. A value of logic 1 allows
the device to respond to I/O space accesses. State after RST# is
logic 0.
RTA
CL
12
R
R
0
4
1
Table
8).
STA
…continued
11
R
0
3
0
-
10
R
0
2
0
-
DEVSELT[1:0]
HS USB PCI Host Controller
reserved
R
9
1
1
0
-
© NXP B.V. 2007. All rights reserved.
ISP1561
MDPE
16 of 103
R
8
0
0
0
-