ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 22

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 19.
[1]
Table 20.
Table 21.
ISP1561_2
Product data sheet
Bit
15 to 0
Bit
7 to 0
Bit
7 to 0
X is 1561h for OHCI1 and OHCI2; X is 1562h for EHCI.
Symbol
IL[7:0]
Symbol
SID[15:0]
Symbol
CP[7:0]
Subsystem ID register: bit description
Capabilities Pointer register: bit description
Interrupt Line register: bit description
8.2.1.14 Subsystem ID register (address: 2Eh)
8.2.1.15 Expansion ROM Base Address register (address: 30h)
8.2.1.16 Capabilities Pointer register (address: 34h)
8.2.1.17 Interrupt Line register (address: 3Ch)
Access
R/W
Access
R
Access
R
Subsystem ID values are vendor-specific. The bit description of the Subsystem ID register
is given in
Some PCI devices, especially those intended for use on expansion boards in the PC
architecture, require local EPROMs for expansion ROM. This 4-byte register at offset 30h
in a type 00h predefined header is defined to handle the base address and size
information for this expansion ROM. The ISP1561 does not support expansion EPROM.
The Capabilities Pointer register is used to point to a linked list of new capabilities
implemented by the device. This register is only valid if the CL bit in the Status register is
set. If implemented, bit 1 and bit 0 are reserved and should be set to 00b. Software must
mask these bits off before using this register as a pointer in configuration space to the first
entry of a linked list of new capabilities. The bit description of the register is given in
Table
The Interrupt Line register is a 1-byte read/write register used to communicate interrupt
line routing information. This register must be implemented by any device or device
function that uses an interrupt pin. The interrupt allocation is done by the BIOS. The
POST software needs to write the routing information into this register because it
initializes and configures the system. The bit description of the Interrupt Line register is
given in
The value in this register specifies which input of the system interrupt controller(s) the
interrupt pin of the device is connected. The device itself does not use this value, rather it
is used by device drivers and operating systems to determine priority and vector
information. Values in this register are system architecture specific.
20.
Value
00h
Value
DCh
Table
Value
X
[1]
Table
21.
19.
Description
Interrupt Line: Indicates which IRQ is used to report interrupt from the
ISP1561.
Description
Capabilities Pointer: EHCI manages power efficiently using this register. This
power management register is allocated at offset DCh. Only one Host
Controller is needed to manage power in the ISP1561.
Description
Subsystem ID: For the ISP1561, NXP Semiconductors has defined OHCI
functions as 1561h, and the EHCI function as 1562h.
Rev. 02 — 5 March 2007
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1561
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