ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 51

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 69.
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcFmInterval register: bit allocation
11.1.14 HcFmInterval register (address: content of the base address register + 34h)
R/W
R/W
R/W
FIT
31
23
15
0
0
0
7
1
-
reserved
The HcFmInterval register contains a 14-bit value that indicates the bit time interval in a
frame, that is, between two consecutive SOFs, and a 15-bit value indicating the full-speed
maximum packet size that the Host Controller may transmit or receive, without causing a
scheduling overrun. The HCD may carry out minor adjustment on the FI (Frame Interval)
by writing a new value over the present at each SOF. This provides the possibility for the
Host Controller to synchronize with an external clocking resource and to adjust any
unknown local clock offset. The bit allocation of the register is given in
Table 70.
Bit
31
30 to 16
15 to 14
13 to 0
R/W
R/W
R/W
30
22
14
0
0
0
6
1
-
HcFmInterval register: bit description
Symbol
FIT
FSMPS[14:0]
-
FI[13:0]
R/W
R/W
R/W
R/W
29
21
13
0
0
1
5
0
Rev. 02 — 5 March 2007
Description
Frame Interval Toggle: The HCD toggles this bit whenever it loads
a new value to Frame Interval.
FS Largest Data Packet: This field specifies a value that is loaded
into the largest data packet counter at the beginning of each frame.
The counter value represents the largest amount of data in bits that
can be sent or received by the Host Controller in a single
transaction at any given time, without causing a scheduling
overrun. The field value is calculated by the HCD.
reserved
Frame Interval: This specifies the interval between two
consecutive SOFs in bit times. The nominal value is set to 11,999.
The HCD must store the current value of this field before resetting
the Host Controller because this causes the field to be reset the
nominal value. The HCD can then restore the stored value on
completing the reset sequence.
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
1
FSMPS[7:0]
FI[7:0]
FSMPS[14:8]
R/W
R/W
R/W
R/W
27
19
11
0
0
1
3
1
FI[13:8]
R/W
R/W
R/W
R/W
26
18
10
0
0
1
2
1
HS USB PCI Host Controller
R/W
R/W
R/W
R/W
25
17
0
0
9
1
1
1
Table
© NXP B.V. 2007. All rights reserved.
ISP1561
69.
R/W
R/W
R/W
R/W
50 of 103
24
16
0
0
8
0
0
1