ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 67

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ISP1561BMUM

Manufacturer Part Number
ISP1561BMUM
Description
IC USB HOST CTRL HI-SPD 128LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1561BMUM

Controller Type
USB Peripheral Controller
Interface
PCI
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
ISP1561BM-T
ISP1561BM-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1561BMUM
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Part Number:
ISP1561BMUM
Manufacturer:
ST
0
NXP Semiconductors
Table 97.
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
CAPLENGTH/HCIVERSION register: bit allocation
11.3.1 CAPLENGTH/HCIVERSION register (address: content of the base address
11.3 EHCI controller capability registers
31
23
15
R
R
R
0
1
0
7
0
-
Table 96.
Other than the OHCI Host Controller, there are some registers in EHCI that define the
capability of EHCI. The address range of these registers is located before the operational
registers.
register + 00h)
The bit allocation of this 4-byte register is given in
Bit
2
1
0
30
22
14
R
R
R
0
0
0
6
0
-
Symbol
FLAG
IN_FULL
OUT_FULL
HceStatus register: bit description
29
21
13
R
R
R
0
0
0
5
0
-
Description
Flag: Nominally used as a system flag by software to indicate a warm or
cold boot.
Input Full: Except for the case of a gate A20 sequence, this bit is set to
logic 1 on an I/O write to address 60h or 64h. While this bit is set to logic 1
and emulation is enabled, an emulation interrupt condition exists.
Output Full: The Host Controller sets this bit to logic 0 on a read of I/O
port 60h. If IRQEN is set, AUX_OUT_FULL (Auxiliary Output Full)
determines which IRQ is activated. While this bit is logic 0 and C_P
(Character Pending) in HceControl is set to logic 1, an emulation interrupt
condition exists.
Rev. 02 — 5 March 2007
HCIVERSION[15:8]
HCIVERSION[7:0]
CAPLENGTH[7:0]
28
20
12
R
R
R
0
1
0
4
0
-
reserved
…continued
27
19
11
R
R
R
0
0
0
3
1
-
Table
97.
26
18
10
R
R
R
0
1
0
2
1
-
HS USB PCI Host Controller
25
17
R
R
R
0
0
9
0
1
0
-
© NXP B.V. 2007. All rights reserved.
ISP1561
66 of 103
24
16
R
R
R
0
1
8
0
0
0
-

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