ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 52

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 71.
Table 73.
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcFmRemaining register: bit allocation
HcFmNumber register: bit allocation
11.1.15 HcFmRemaining register (address: content of the base address register +
11.1.16 HcFmNumber register (address: content of the base address register + 3Ch)
FRT
R/W
R/W
31
23
15
31
0
0
0
7
0
0
-
-
-
reserved
38h)
The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in
the current frame.
Table 72.
This register is a 16-bit counter, and the bit allocation is given in
timing reference among events happening in the Host Controller and the HCD. The HCD
may use the 16-bit value specified in this register and generate a 32-bit frame number
without requiring frequent access to the register.
Bit
31
30 to 14
13 to 0
R/W
30
22
14
30
0
0
0
6
0
0
-
-
-
-
Symbol
FRT
-
FR[13:0]
HcFmRemaining register: bit description
Table 71
R/W
R/W
29
21
13
29
0
0
0
5
0
0
-
-
-
Description
Frame Remaining Toggle: This bit is loaded from the FIT (Frame Interval
Toggle) field of HcFmInterval whenever FR (Frame Remaining) reaches 0.
This bit is used by the HCD for the synchronization between FI (Frame
Interval) and FR.
reserved
Frame Remaining: This counter is decremented at each bit time. When it
reaches 0, it is reset by loading the FI value specified in HcFmInterval at
the next bit time boundary. When entering the USBOPERATIONAL state,
the Host Controller reloads the content with the FI of HcFmInterval and
uses the updated value from the next SOF.
Rev. 02 — 5 March 2007
contains the bit allocation of this four-byte register.
R/W
R/W
28
20
12
28
0
0
0
4
0
0
-
-
-
reserved
reserved
FR[7:0]
reserved
R/W
R/W
27
19
11
27
0
0
0
3
0
0
-
-
-
FR[13:8]
R/W
R/W
26
18
10
26
0
0
0
2
0
0
-
-
-
HS USB PCI Host Controller
Table
R/W
R/W
25
17
25
0
0
9
0
1
0
0
73. It provides a
-
-
-
© NXP B.V. 2007. All rights reserved.
ISP1561
R/W
R/W
51 of 103
24
16
24
0
0
8
0
0
0
0
-
-
-