ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 82

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
ISP1561_2
Product data sheet
Table 119. PORTSC 1, 2, 3, 4 register: bit description
Bit
9
8
7
Symbol
-
PR
SUSP
Description
reserved
Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not
in reset. Default = 0. When software sets this bit from logic 0, the bus reset
sequence as defined in
Software clears this bit to terminate the bus reset sequence. Software must
hold this bit at logic 1 until the reset sequence, as specified in
“Universal Serial Bus
Remark: When software sets this bit, it must also clear the Port Enable bit.
Remark: When software clears this bit, there may be a delay before the bit
status changes to logic 0 because it will not read logic 0 until the reset is
completed. If the port is in high-speed mode after reset is completed, the
Host Controller will automatically enable this port; it can set the Port Enable
bit. A Host Controller must terminate the reset and stabilize the state of the
port within 2 ms of software changing this bit from logic 1 to logic 0. For
example, if the port detects that the attached device is high-speed during a
reset, then the Host Controller must enable the port within 2 ms of software
clearing this bit.
The HCH (HC Halted) bit in the USBSTS register must be logic 0 before
software attempts to use this bit. The Host Controller may hold Port Reset
asserted when the HCH (HC Halted) bit is set.
Suspend: Default = 0. A logic 1 means the port is in the suspend state. A
logic 0 means the Port is not suspended. The Port Enabled bit and the
Suspend bit of this register define the port states as follows:
PED = 0 and SUSP = x — Port is disabled
PED = 1 and SUSP = 0 — Port is enabled
PED = 1 and SUSP = 1 — Port is suspended
When in the suspend state, downstream propagation of data is blocked on
this port, except for the port reset. If a transaction was in progress when this
bit was set, blocking occurs at the end of the current transaction. In the
suspend state, the port is sensitive to resume detection. The bit status does
not change until the port is suspended and there may be a delay in
suspending a port, if there is a transaction currently in progress on USB.
Attempts to clear this bit are ignored by the Host Controller. The Host
Controller will unconditionally set this bit to logic 0 when:
If the host software sets this bit when the Port Enabled bit is logic 0, the
results are undefined.
•
•
Rev. 02 — 5 March 2007
Software changes the FPR (Force Port Resume) bit to logic 0.
Software changes the PR (Port Reset) bit to logic 1.
Specification”, is completed.
[1]
Ref. 8 “Universal Serial Bus Specification”
…continued
HS USB PCI Host Controller
[1]
© NXP B.V. 2007. All rights reserved.
ISP1561
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