ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 50

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 67.
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcDoneHead register: bit allocation
11.1.13 HcDoneHead register (address: content of the base address register + 30h)
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 66.
The HcDoneHead register contains the physical address of the last completed TD that
was added to the done queue. In a normal operation, the HCD need not read this register
because its content is periodically written to the HCCA.
of the register.
Table 68.
Bit
31 to 4
3 to 0
Bit
31 to 4
3 to 0
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Symbol
BCED[27:0]
-
HcBulkCurrentED register: bit description
HcDoneHead register: bit description
DH[3:0]
Symbol
DH[27:0]
-
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Description
Bulk Current ED: This is advanced to the next ED after the Host
Controller has served the present ED. The Host Controller continues
processing the list from where it left off in the last frame. When it reaches
the end of the bulk list, the Host Controller checks the CLF (Control List
Filled) bit of HcControl. If the CLF bit is not set, nothing is done. If the CLF
bit is set, it copies the content of HcBulkHeadED to HcBulkCurrentED and
clears the CLF bit. The HCD can only modify this register when the BLE
(Bulk List Enable) bit of HcControl is cleared. When HcControl is set, the
HCD reads the instantaneous value of this register. This is initially set to
logic 0 to indicate the end of the bulk list.
reserved
Rev. 02 — 5 March 2007
Description
Done Head: When a TD is completed, the Host Controller writes the
content of HcDoneHead to the NextTD field of the TD. The Host
Controller then overwrites the content of HcDoneHead with the
address of this TD. This is set to logic 0 whenever the Host Controller
writes the content of this register to HCCA.
reserved
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
DH[27:20]
DH[19:12]
DH[11:4]
R/W
R/W
R/W
27
19
11
0
0
0
3
0
-
Table 67
R/W
R/W
R/W
26
18
10
0
0
0
2
0
-
HS USB PCI Host Controller
reserved
contains the bit allocation
R/W
R/W
R/W
25
17
0
0
9
0
1
0
-
© NXP B.V. 2007. All rights reserved.
ISP1561
R/W
R/W
R/W
49 of 103
24
16
0
0
8
0
0
0
-