ISP1561BMUM ST-Ericsson Inc, ISP1561BMUM Datasheet - Page 73

• Manufacturer Part Number: ISP1561BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1561BMUM

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1561BM-T; ISP1561BM-T

NXP Semiconductors
Table 105. USBSTS register: bit allocation
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
11.4.2 USBSTS register (address: content of the base address register + 10h)
ASS
31
23
15
R
0
0
0
7
0
-
-
-
reserved
The USB Status (USBSTS) register indicates pending interrupts and various states of the
Host Controller. The status resulting from a transaction on the serial bus is not indicated in
this register. Software clears the register bits by writing ones to them. The bit allocation is
given in
Table 106. USBSTS register: bit description
Bit
31 to 16
15
14
13
PSSTAT
30
22
14
R
0
0
0
6
0
-
-
-
Table
Symbol
-
ASS
PSSTAT
RECL
105.
RECL
IAA
29
21
13
R
R
0
0
0
5
0
-
-
Rev. 02 — 5 March 2007
Description
reserved
Asynchronous Schedule Status: 0 = Default. The bit reports the
current real status of the asynchronous schedule. If this bit is logic 0,
the status of the asynchronous schedule is disabled. If this bit is
logic 1, the status of the asynchronous schedule is enabled. The
Host Controller is not required to immediately disable or enable the
asynchronous schedule when software changes the ASE
(Asynchronous Schedule Enable) bit in the USBCMD register. When
this bit and the ASE (Asynchronous Schedule Enable) bit have the
same value, the asynchronous schedule is either enabled (1) or
disabled (0).
Periodic Schedule Status: 0 = Default. This bit reports the current
status of the periodic schedule. If this bit is logic 0, the status of the
periodic schedule is disabled. If this bit is logic 1, the status of the
periodic schedule is enabled. The Host Controller is not required to
immediately disable or enable the periodic schedule when software
changes the PSE (Periodic Schedule Enable) bit in the USBCMD
register. When this bit and the PSE bit have the same value, the
periodic schedule is either enabled (1) or disabled (0).
Reclamation: 0 = Default. This is a read-only status bit that is used
to detect an empty asynchronous schedule.
HCH
HSE
R/W
28
20
12
R
0
0
1
4
0
-
-
reserved
reserved
R/W
FLR
27
19
11
0
0
0
3
0
-
-
-
PCD
R/W
26
18
10
0
0
0
2
0
-
-
-
HS USB PCI Host Controller
reserved
ERRINT
USB
R/W
25
17
0
0
9
0
1
0
-
-
-
© NXP B.V. 2007. All rights reserved.
ISP1561
USBINT
R/W
72 of 103
24
16
0
0
8
0
0
0
-
-
-