DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 92

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 4: Receive FIFO High Watermark (RHWM). This read-only real-time status bit will be set to a one when the
receive FIFO contains more than the number of bytes configured by the Receive High Watermark Setting control
bits (RHWMS0 to RHWMS2) in the HDLC Control Register (HCR). This bit will be cleared when the FIFO
empties below the high watermark. The setting of this bit can cause a hardware interrupt to occur if the RHWM bit
in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR
(IMSR) register is set to a one.
Bit 5: Receive Packet Start (RPS). This latched read-only event-status bit will be set to a one each time the
HDLC controller detects an opening byte of an HDLC packet. This bit will be cleared when read and will not be set
again until another message is detected. The setting of this bit can cause a hardware interrupt to occur if the RPS bit
in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR
(IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
Bit 6: Receive Packet End (RPE). This latched read-only event-status bit will be set to a one each time the HDLC
controller detects the finish of a message whether the packet is valid (CRC correct) or not (bad CRC, abort
sequence detected, packet too small, not an integral number of octets, or an overrun occurred). This bit will be
cleared when read and will not be set again until another message end is detected. The setting of this bit can cause a
hardware interrupt to occur if the RPE bit in the Interrupt Mask for HSR (IHSR) register is set to a one and the
HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear
when this bit is read.
Bit 7: Transmit FIFO Underrun (TUDR). This latched read-only event-status bit will be set to a one each time
the transmit FIFO underruns and an abort is automatically sent. This bit will be cleared when read and will not be
set again until another underrun occurs (i.e., the FIFO has been written to and then allowed to empty again). The
setting of this bit can cause a hardware interrupt to occur if the TUDR bit in the Interrupt Mask for HSR (IHSR)
register is set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read.
Bits 8 to 11: Transmit FIFO Level Bits 0 to 3 (TFL0 to TFL3). These read-only real-time status bits indicate the
current depth of the transmit FIFO with a 16-byte resolution. These status bits cannot cause a hardware interrupt.
Bit 12: Transmit FIFO Empty (TEMPTY). This read-only real-time status bit will be set to a one when the
transmit FIFO is empty. It will be cleared when the transmit FIFO contains one or more bytes. This status bit
cannot cause a hardware interrupt.
Bit 13: Receive FIFO Overrun (ROVR). This latched read-only event-status bit will be set to a one each time the
receive FIFO overruns. This bit will be cleared when read and will not be set again until another overrun occurs
TFL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TFL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TFL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TFL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
92 of 133
TRANSMIT FIFO LEVEL
empty to 15 bytes
112 to 127 bytes
128 to 143 bytes
144 to 159 bytes
160 to 175 bytes
176 to 191 bytes
192 to 207 bytes
208 to 223 bytes
224 to 239 bytes
240 to 256 bytes
96 to 111 bytes
16 to 31 bytes
32 to 47 bytes
48 to 63 bytes
64 to 79 bytes
80 to 95 bytes
DS3112