DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 58

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 5: Severely Errored Framing Event Detected (SEFE). This latched read-only event-status bit will be set to a
one each time the DS3112 has detected either three or more F bits in error out of 16 consecutive F bits (T3 mode)
or four bad FAS words in a row (E3 mode). This bit will be cleared when read and will not be set again until the
device detects another SEFE event.
Bit 8: E3 National Bit (E3Sn). This read-only real-time status bit reports the incoming E3 National Bit (Sn). It is
loaded at the start of each E3 frame as the Sn bit is decoded. The host can use the RSOF status bit in the T3/E3
Status Register (T3E3SR) to determine when to read this bit.
Bit 9: T3 Application ID Channel Status (T3AIC). This read-only real-time status bit can be used to help
determine whether an incoming T3 data stream is in C-Bit Parity mode or M23 mode. In C-Bit Parity mode, it is
recommended that the first C bit in each M frame be set to one. In M23 mode, the first C bit in each M frame
should be toggling between zero and one to indicate that the bits need to be stuffed or not. This bit will be set to a
one when the device detects that the first C bit in the M frame is set to one for 1020 times or more out of 1024
consecutive M frames (109ms). It will be allowed to be cleared when the device detects that the first C bit is set to
one less than 1020 times out of 1024 consecutive M frames (109ms). This status bit has no meaning in the E3 mode
and should be ignored.
Bit 10: Loss Of Signal Clear Detected (LOSC). This latched read-only event-status bit will be set to a one each
time the T3/E3 framer exits a Loss Of Signal (LOS) state. This bit will be cleared when read and will not be set
again until the device once again exits the LOS state. The LOS alarm criteria are described in
Table
Bit 11: Loss Of Frame Clear Detected (LOFC). This latched read-only event-status bit will be set to a one each
time the T3/E3 framer exits a Loss Of Frame (LOF) state. This bit will be cleared when read and will not be set
again until the device once again exits the LOF state. The LOF alarm criteria are described in
Table
Bit 12: Alarm Indication Signal Clear Detected (AISC). This latched read-only event status bit will be set to a
one each time the T3/E3 framer no longer detects the AIS alarm state. This bit will be cleared when read and will
not be set again until the device once again exits the AIS alarm state. The AIS alarm criteria is described in
Table 5-1
ANSI T1.231.
Bit 13: Remote Alarm Indication Clear Detected (RAIC). This latched read-only event-status bit will be set to a
one each time the T3/E3 framer no longer detects the RAI alarm state. This bit will be cleared when read and will
not be set again until the device once again exits the RAI alarm state. The RAI alarm criteria are described in
Table 5-1
ANSI T1.231.
5-2. This status bit is useful in helping the host determine if the LOS persists as defined in ANSI T1.231.
5-2. This status bit is useful in helping the host determine if the LOF persists as defined in ANSI T1.231.
and
and
Table
Table
5-2. This status bit is useful in helping the host determine if the RAI persists as defined in
5-2. This status bit is useful in helping the host determine if the AIS persists as defined in
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Table 5-1
Table 5-1
DS3112
and
and