DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 60

IC MUX T3/E3 3.3V 256-PBGA

DS3112+W

Manufacturer Part Number
DS3112+W
Description
IC MUX T3/E3 3.3V 256-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3112+W

Controller Type
Framer, Multiplexer
Interface
Parallel/Serial
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
150mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: 16-Bit Framing Bit Error Counter (FE0 to FE15). These bits report either the number of Loss Of
Frame (LOF) occurrences or the number of framing bit errors received. The FECR is configured via the host by the
Frame Error Counting Control Bits (FECC0 and FECC1) in the T3E3 Control Register (Section 5.2). The possible
configurations are shown below.
When the FECR is configured to count LOF occurrences, the FECR increments by one each time the device loses
receive synchronization. When the FECR is configured to count framing bit errors, it can be configured via the
ECC control bit in the T3/E3 Control Register (Section 5.2) to either continue counting frame bit errors during a
LOF or not.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15:16-Bit T3 Parity Bit Error Counter (PE0 to PE15). These bits report the number of T3 parity bit
errors. In the E3 mode, this counter is meaningless and should be ignored. A parity bit error is defined as an
occurrence when the two parity bits do not match one another or when the two Parity Bits do not match the parity
calculation made on the information bits. Via the ECC control bit in the T3/E3 Control Register (Section 5.2), the
PCR can be configured to either continue counting parity bit errors during a LOF or not.
FECC1
0
0
1
1
FECC0
PE15
FE15
PE7
FE7
15
15
7
7
0
1
0
1
T3 Mode: Count Loss Of Frame (LOF) Occurrences
E3 Mode: Count Loss Of Frame (LOF) Occurrences
T3 Mode: Count both F Bit and M Bit Errors
E3 Mode: Count Bit Errors in the FAS Word
T3 Mode: Count Only F Bit Errors
E3 Mode: Count Word Errors in the FAS Word
T3 Mode: Count only M Bit Errors
E3 Mode: Illegal State
PE14
FE14
FRAME ERROR COUNT REGISTER (FECR)
PE6
FE6
14
14
6
6
FECR
Frame Error Count Register
24h
PCR
T3 Parity Bit Error Count Register
26h
PE13
FE13
PE5
FE5
13
13
5
CONFIGURATION
5
60 of 133
PE12
FE12
PE4
FE4
12
12
4
4
PE11
FE11
PE3
FE3
11
11
3
3
PE10
PE2
FE10
FE2
10
2
10
2
PE1
PE9
FE1
FE9
1
9
1
9
PE0
PE8
FE0
FE8
0
8
DS3112
0
8

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