DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 66

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: See
other bits are read-write.
Bits 0 to 6: Remote Alarm Indication Signal Detected (RAIn when n = 1 to 7). This latched read-only alarm-
status bit will be set to a one each time the corresponding T2/E2/G.747 framer detects an incoming RAI alarm.
This bit will be cleared when read unless the RAI alarm still exists in that T2/E2/G.747 framer. A change in state of
the RAI in one or more of the T2/E2/G.747 framers can cause the T2E2SR2 status bit (in the MSR register) to be
set and a hardware interrupt to occur if the IERAI bit is set to a one and the T2E2SR2 bit in the Interrupt Mask for
MSR (IMSR) register is set to a one
RAI alarm criteria are described in
are meaningless and should be ignored.
Bit 7: Interrupt Enable for Remote Alarm Indication Signal (IERAI). This bit should be set to one if the host
wishes to have RAI detection occurrences cause a hardware interrupt or the setting of the T2E2SR2 status bit in the
MSR register
also be set to one for an interrupt to occur.
Bits 8 to 11: E2 Receive National Bit (E2Snn when n = 1 to 4). This read-only real-time status bit reports the
incoming E2 National Bit (Sn). It is loaded at the start of each E2 frame as the Sn bit is decoded. The host can use
the E2SOF status bit to determine when to read this bit. In the T3 and G.747 modes, this bit is meaningless and
should be ignored. This bit cannot cause an interrupt to occur.
Bits 12 to 15: E2 Receive Start Of Frame (E2SOFn where n = 1 to 4). This latched read-only event-status bit
will be set to a one on each E2 receive frame boundary. This bit will be cleared when read. The setting of this
status bit cannot cause an interrupt to occur.
Figure 6-2. T2E2SR2 Status Bit Flow
0 = interrupt masked
1 = interrupt unmasked
Figure 6-2
Internal RAI
Signal from
T2/E2 Framer 1
Internal RAI
Signal from
T2/E2 Framer 2
Internal RAI
Signal from
T2 Framer 7
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE T2E2SR2 REGISTER IS READ.
E2SOF4
(Figure
IERAI
15
—
7
0
for details on the signal flow for the status bits in the T2E2SR2 register. Bits that are underlined are read-only; all
6-2). The T2E2SR2 bit in the Interrupt Mask for the Master Status Register (IMSR) must
E2SOF3
RAI7
—
14
—
Change in State Detect
Change in State Detect
Change in State Detect
Alarm Latch
Alarm Latch
Alarm Latch
6
T2E2SR2
T2/E2 Status Register 2
36h
Table
(Figure
E2SOF2
RAI6
6-1,
—
13
—
5
RAI1
(T2E2SR2
Bit 0)
RAI2
(T2E2SR2
Bit 1)
RAI7
(T2E2SR2
Bit 6)
6-2). The interrupt will be allowed to clear when this bit is read. The
Table
Event Latch
Event Latch
Event Latch
6-2, and
E2SOF1
66 of 133
RAI5
—
12
—
4
Table
OR
E2Sn4
RAI4
6-3. In the E3 mode, RAI5 to RAI7 (bits 4 to 6)
—
11
—
3
IERAI
(T2E2SR2
Bit 7)
Mask
E2Sn3
RAI3
—
10
—
2
T2E2SR2
(IMSR Bit 6)
Mask
E2Sn2
RAI2
—
—
1
9
T2E2SR2
Status Bit
(MSR Bit 6)
INT*
Hardware
Signal
E2Sn1
RAI1
—
—
DS3112
0
8