DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 89

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 5: Transmit HDLC Reset (THR). A zero to one transition will reset the Transmit HDLC controller. Must be
cleared and set again for a subsequent reset. A reset will flush the current contents of the transmit FIFO and cause
one FEh abort sequence (7 ones is a row) to be sent followed by either 7Eh (flags) or FFh (idle) until a new packet
is initiated by writing new data (at least 2 bytes) into the FIFO.
Bit 6: Receive HDLC Reset (RHR). A zero to one transition will reset the Receive HDLC controller. Must be
cleared and set again for a subsequent reset. A reset will flush the current contents of the receive FIFO and cause
the receive HDLC controller to begin searching for a new incoming HDLC packet.
Bit 8: Transmit Invert Data (TID). The control bit determines whether all of the data from the HDLC controller
(including flags and CRC checksum) will be inverted after processing.
Bit 9: Receive Invert Data (RID). The control bit determines whether all of the data into the HDLC controller
(including flags and CRC checksum) will be inverted before processing.
Bits 10 to 12: Transmit Low Watermark Select Bits (TLWMS0 to TLWMS2). These control bits determine
when the HDLC controller should set the TLWM status bit in the HDLC Status Register (HSR). When the transmit
FIFO contains less than the number of bytes configured by these bits, the TLWM status bit will be set to a one.
Bits 13 to 15: Receive High Watermark Select Bits (RHWMS0 to RHWMS2). These control bits determine
when the HDLC controller should set the RHWM status bit in the HDLC Status Register (HSR). When the receive
FIFO contains more than the number of bytes configured by these bits, the RHWM status bit will be set to a one.
RHWMS2
TLWMS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0 = do not invert data (normal operation)
1 = invert all data
0 = do not invert data (normal operation)
1 = invert all data
RHWMS1
TLWMS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TLWMS0
RHWMS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
WATERMARK (bytes)
WATERMARK (bytes)
TRANSMIT LOW
RECEIVE HIGH
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112
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240
16
48
80
DS3112