DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 57

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5-2. E3 Alarm Criteria
Note: LOS is not defined for unipolar (binary) operation.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write. The status bits in the T3E3INFO cannot cause a hardware
interrupt to occur.
Bit 0: Change Of Frame Alignment Detected (COFA). This latched read-only event-status bit will be set to a
one when the T3/E3 framer has experienced a change of frame alignment (COFA). A COFA occurs when the
device achieves synchronization in a different alignment than it had previously. If the device has never acquired
synchronization before, then this status bit is meaningless. This bit will be cleared when read and will not be set
again until the framer has lost synchronization and reacquired synchronization in a different alignment.
Bit 1: Zero Suppression Codeword Detected (ZSCD). This latched read-only event-status bit will be set to a one
when the T3/E3 framer has detected a B3ZS/HDB3 codeword. This bit will be cleared when read and will not be
set again until the framer has detected another B3ZS/HDB3 codeword.
Bit 2: F-Bit or FAS Error Detected (FBE). This latched read-only status bit will be set to a one when the DS3112
has detected an error in either the F bits (T3 mode) or the FAS word (E3 mode). This bit will be cleared when read
and will not be set again until the device detects another error.
Bit 3: M-Bit Error Detected (MBE). This latched read-only event status bit will be set to a one when the DS3112
has detected an error in the M bits. This bit will be cleared when read and will not be set again until the device
detects another error in one of the M bits. This status bit has no meaning in the E3 mode and should be ignored.
Bit 4: Excessive Zeros Detected (EXZ). This latched read-only event status bit will be set to a one each time the
DS3112 has detected a consecutive string of either three or more zeros (T3 mode) or four or more zeros (E3 mode).
This bit will be cleared when read and will not be set again until the device detects another EXcessive Zero event.
CONDITION
ALARM/
LOS
LOF
RAI
AIS
—
—
15
—
—
7
Alarm Indication Signal
Unframed all ones
Loss Of Signal
(See note)
Loss Of Frame
Too many FAS errors
Remote Alarm Indication
Inactive: Bit 11 of the frame = 0
Active: Bit 11 of the frame = 1
DEFINITION
—
—
14
—
—
6
T3E3INFO
T3/E3 Information Register
16h
SEFE
RAIC
—
13
—
5
57 of 133
AISC
EXZ
—
12
—
Four or fewer zeros in
two consecutive 1536-
bit frames
192 consecutive zeros
Four consecutive bad
FAS
Bit 11 = 1 for 4
consecutive frames
(6144 bits/179µs)
4
SET CRITERIA
LOFC
MBE
—
11
—
3
LOSC
FBE
—
10
—
2
Five or more zeros in two
consecutive 1536-bit frames
No EXZ events over a 192-bit
window that starts with the
first one received
Three consecutive good FAS
Bit 11 = 0 for 4 consecutive
frames (6144 bits/179µs)
CLEAR CRITERIA
T3AIC
ZSCD
—
—
1
9
COFA
E3Sn
—
—
DS3112
0
8