DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 86

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-1. BERT Status Bit Flow
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: BERT 24-Bit Error Counter (BEC8 to BEC23). Upper two bytes of the 24-bit counter. This 24-bit
counter will increment for each data bit received in error. This counter is not disabled when the receive BERT loses
synchronization. This counter can be cleared by toggling the LC control bit in BERTBC0. This counter saturates
and will not rollover. Upon saturation, the BECO status bit in the BERTEC0 register will be set. This error counter
starts counting when the BERT goes into receive synchronization (RLOS = 0 or SYNC = 1) and it will not stop
counting when the BERT loses synchronization. It is recommended that the host toggle the LC bit in BERTC0
register once the BERT has synchronized and then toggle the LC bit again when the error checking period is
complete. If the device loses synchronization during this period, then the counting results are suspect.
Internal RLOS
Signal from
BERT
Internal Bit
Error Detected
Signal from
BERT
Internal Counter
Overflow
Signal from
BERT
BEC15
BEC23
15
7
0
0
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE BERTEC0 REGISTER IS READ.
BEC14
BEC22
14
6
0
0
Change in State Detect
Alarm Latch
Event Latch
Event Latch
BERTEC1
BERT 24-Bit Error Counter (upper)
7Eh
IESYNC (BERTC0 Bit 15)
BEC13
BEC21
13
5
0
0
IEBED (BERTC0 Bit 14)
RLOS
(BERTEC0
Bit 4)
BED
(BERTEC0
Bit 3)
BECO or BBCO
(BERTEC0
Bits 1 & 2)
IEOF (BERTC0 Bit 13)
Event Latch
BEC12
BEC20
86 of 133
12
4
0
0
Mask
Mask
Mask
BEC11
BEC19
11
3
0
0
OR
BEC10
BEC18
10
2
0
0
BERT
(IMSR Bit 2)
Mask
BEC17
BEC9
1
9
0
0
BERT
Status Bit
(MSR Bit 2)
INT*
Hardware
Signal
BEC16
BEC8
DS3112
0
0
8
0