DS3112+W Maxim Integrated Products, DS3112+W Datasheet
DS3112+W
Specifications of DS3112+W
Related parts for DS3112+W
DS3112+W Summary of contents
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FEATURES Operates as M13 or E13 Multiplexer or as Stand-Alone Framer Flexible Multiplexer can be Programmed for Multiple Configurations Including: M13 Multiplexing (28 T1 Lines into a T3 Data Stream) E13 Multiplexing (16 E1 Lines into ...
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DETAILED DESCRIPTION 1 PPLICABLE TANDARDS 1.2 M DS3112 TEMPE F AIN 1.2.1 General Features ................................................................................................................................... 9 1.2.2 T3/E3 Framer ......................................................................................................................................... 9 1.2.3 T2/E2 Framer ......................................................................................................................................... 9 1.2.4 HDLC Controller..................................................................................................................................... 9 1.2.5 FEAC Controller ..................................................................................................................................... 9 1.2.6 BERT.................................................................................................................................................... ...
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INE OOPBACK 7.7 T1/ ROP AND NSERT 8 BERT 8.1 BERT R D EGISTER ESCRIPTION 9 HDLC CONTROLLER 9 ECEIVE PERATION 9 RANSMIT PERATION 9.2 HDLC C ONTROL AND ...
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E13 B .............................................................................................................................128 ASICS 14 RAMING TRUCTURE AND 14. RAMING TRUCTURE AND 14.11 G.747 B ......................................................................................................................131 ASICS 14.12 G.747 F S RAMING 15 PACKAGE INFORMATION 15.1 256-B PBGA (56-G6002-001)............................................................................................133 ALL E12 M ....................................................................129 ...
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Figure 1-1. DS3112 Framer and Multiplexer Block Diagram (T3 Mode) ................................................................... 11 Figure 1-2. DS3112 Framer and Multiplexer Block Diagram (E3 Mode)................................................................... 12 Figure 1-3. DS3112 Framer and Multiplexer Block Diagram (G.747 Mode) ............................................................. 13 Figure 2-1. T3/E3 Receive Framer ...
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Table 2-1. Pin Naming Convention............................................................................................................................ 14 Table 2-2. Pin Description ......................................................................................................................................... 14 Table 2-3. Mode Select Decode ................................................................................................................................ 30 Table 3-1. Memory Map............................................................................................................................................. 31 Table 5-1. T3 Alarm Criteria ...................................................................................................................................... 56 Table 5-2. E3 Alarm Criteria ...................................................................................................................................... 57 Table 6-1. ...
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DETAILED DESCRIPTION The DS3112 TEMPE (T3 E3 MultiPlexEr) device can be used either as a multiplexer or a T3/E3 framer. When the device is used as a multiplexer, it can be operated in one of three modes: M13—Multiplex 28 ...
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Applicable Standards 1) American National Standard for Telecommunications - ANSI T1.107 – 1995 “Digital Hierarchy - Formats Specification” 2) American National Standard for Telecommunications - ANSI T1.231 - 199X – Draft “Digital Hierarchy - Layer 1 In-Service Digital Transmission ...
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Main DS3112 TEMPE Features 1.2.1 General Features Can be operated as a standalone framer without any M13 or E13 multiplexing T1/E1 FIFOs in the receive direction provide T1/E1 demultiplexed clocks with very little jitter Two T1/E1 ...
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BERT Can generate and detect the pseudorandom patterns of 2 repetitive patterns from bits in length BERT is a global chip resource that can be used either in the T3/E3 data path or in any one ...
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Figure 1-1. DS3112 Framer and Multiplexer Block Diagram (T3 Mode) T3 Formatter T3 Framer Error Counters CA0 to CD0 to CWR* FRMECU CA7 CD15 (CR/W*) Signal HRCLK Inversion Loss Of Transmit Clock Control Mux ...
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Figure 1-2. DS3112 Framer and Multiplexer Block Diagram (E3 Mode) E3 Formatter E3 Framer Error Counters CA0 to CD0 to CWR* FRMECU CA7 CD15 (CR/W*) Signal HRCLK Inversion Loss Of Transmit Clock Control Mux ...
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Figure 1-3. DS3112 Framer and Multiplexer Block Diagram (G.747 Mode) T3 Formatter T3 Framer Error Counters FRMECU CA0 to CD0 to CWR* CA7 CD15 (CR/W*) Signal HRCLK Inversion Loss Of Transmit Clock Control Mux ...
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PIN DESCRIPTION This section describes the input and output signals on the DS3112. Signal names follow a convention that is shown in Table 2-1. Table 2-2 Table 2-1. Pin Naming Convention FIRST SIGNAL CATEGORY LETTERS C CPU/Host Control Access ...
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PIN NAME TYPE CRD(CDS) D5 CWR A3 (CR/W) A9 FRCLK B9 FRD C9 FRDEN C8 FRLOF B8 FRLOS A7 FRMECU A8 FRSOF A10 FTCLK B10 FTD C10 FTDEN C11 FTMEI A11 FTSOF B6 G.747E A13 HRCLK C12 HRNEG B13 HRPOS ...
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PIN NAME TYPE W14 LRCLK15 Y16 LRCLK16 Y17 LRCLK17 U16 LRCLK18 V18 LRCLK19 V19 LRCLK20 V20 LRCLK21 T20 LRCLK22 R20 LRCLK23 N18 LRCLK24 M18 LRCLK25 L18 LRCLK26 K18 LRCLK27 H20 LRCLK28 K1 LRCLKA M1 LRCLKB N1 LRDAT1 P2 LRDAT2 P4 ...
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PIN NAME TYPE G19 LTCCLK P1 LTCLK1 R2 LTCLK2 U1 LTCLK3 T4 LTCLK4 V3 LTCLK5 V4 LTCLK6 V5 LTCLK7 U7 LTCLK8 W7 LTCLK9 Y8 LTCLK10 Y9 LTCLK11 Y11 LTCLK12 W12 LTCLK13 V13 LTCLK14 V14 LTCLK15 V15 LTCLK16 W17 LTCLK17 W18 ...
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PIN NAME U14 LTDAT16 V16 LTDAT17 V17 LTDAT18 W19 LTDAT19 U19 LTDAT20 U20 LTDAT21 R18 LTDAT22 P18 LTDAT23 N19 LTDAT24 M19 LTDAT25 L20 LTDAT26 J20 LTDAT27 H19 LTDAT28 L1 LTDATA M2 LTDATB A6, A12, A15– A20, B1, B7, B11, B12, ...
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CPU Bus Signal Description Signal Name: CMS Signal Description: CPU Bus Mode Select Signal Type: Input This signal should be tied low when the device operated as a 16-bit bus. This signal should be tied high ...
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CINT Signal Name: Signal Description: CPU Bus Interrupt Signal Type: Output (Open Drain) This signal is an open-drain output that will be forced low if one or more unmasked interrupt sources within the device is active. The signal will remain ...
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T3/E3 Receive Framer Signal Description Signal Name: FRSOF Signal Description: T3/E3 Receive Framer Start Of Frame Sync Signal Signal Type: Output This signal pulses for one FRCLK period to indicate the frame boundary signal can be ...
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Signal Name: FRLOS Signal Description: T3/E3 Receive Framer Loss Of Signal Signal Type: Output This signal will be forced high when the receive T3/E3 framer Loss Of Signal (LOS) state. It will remain high as long as ...
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T3/E3 Transmit Formatter Signal Description Signal Name: FTSOF Signal Description: T3/E3 Transmit Formatter Start Of Frame Sync Signal Signal Type: Output/Input This signal can be configured via the FTSOFC control bit in Master Control Register either ...
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Signal Name: FTMEI Signal Description: T3/E3 Transmit Formatter Manual Error Insert Strobe Signal Type: Input Via the EIC control bit in the T3/E3 Error Insert Control Register (Section 5.2), the DS3112 can be configured to use this asynchronous input to ...
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Low-Speed (T1 or E1) Receive Port Signal Description Signal Name: LRDAT1 to LRDAT28 Signal Description: Low-Speed (T1 or E1) Receive Serial Data Outputs Signal Type: Output These output signals present the demultiplexed serial data for the 28 T1 data ...
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Signal Name: LRCCLK Signal Description: Low-Speed (T1 or E1) Receive Common Clock Input Signal Type: Input If enabled via the LRCCEN control bit in Master Control Register 1 (Section 4.2), all 28 LRCLK or 16/21 LRCLK can be slaved to ...
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Signal Name: LTDATA/LTDATB Signal Description: Low-Speed (T1 or E1) Transmit Insert Port Serial Data Inputs Signal Type: Input These two input signals allow data to be inserted in place of any of the 28 T1 data streams or into any ...
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High-Speed (T3 or E3) Receive Port Signal Description Signal Name: HRPOS/HRNEG Signal Description: High-Speed (T3 or E3) Receive Serial Data Inputs Signal Type: Input These input signals sample the serial data from the incoming T3 data streams or E3 ...
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JTAG Signal Description Signal Name: JTCLK Signal Description: JTAG IEEE 1149.1 Test Serial Clock Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If ...
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Signal Name: T3E3MS Signal Description: T3/E3 Mode Select Input Signal Type: Input This signal determines whether the DS3112 will operate in either the T3 mode or the E3 mode. It acts as a global control bit for the entire DS3112. ...
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MEMORY MAP Table 3-1. Memory Map ADDRESS ACRONYM R/W 00 MRID R/W 02 MC1 R/W 04 MC2 R/W 06 MC3 R/W 08 MSR 0A IMSR R/W 0C TEST R/W 10 T3E3CR R/W 12 T3E3SR 14 IT3E3SR R/W 16 T3E3INFO ...
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ADDRESS ACRONYM R/W 82 RHDLC 84 THDLC 86 HSR 88 IHSR R/W 90 FCR R/W 92 FSR 38, 48, 64, 66, 68, 94, 96, 98, 0E, 1A, 1C, 1E, 2C, 2E, 3A, — 3C, 3E, 4A, 4C, 4E, 6A, 6C, ...
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MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT 4.1 Master Reset and ID Register Description The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set to one, all of the internal ...
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Master Configuration Registers Description Register Name: Register Description: Register Address: Bit # 7 6 Name FTSOFC LOTCMC Default 0 0 Bit # 15 14 Name — — Default — — Note: Bits that are underlined are read-only; all other ...
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Bit 4: Manual Error Counter Update (MECU). A zero to one transition on this bit will cause the device to update the performance error counters. This bit is ignored if the AECU control bit is set low. This bit must ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default — — Bit # 15 14 Name — — Default — — Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name FRSOFI FRCLKI Default 0 0 Bit # 15 14 Name — — Default — — Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: ...
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Master Status and Interrupt Register Description 4.3.1 Status Registers The status registers in the DS3112 allow the host to monitor the real-time condition of the device. Most of the status bits in the device can cause a hardware interrupt ...
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Figure 4-3. Real-Time Status Bit Internal Signal Status Bit Interrupt Read 4.3.2 MSR The Master Status Register (MSR special status register that can be used to help the host quickly locate changes in device status. There is a ...
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This bit will be cleared when the BERTEC0 is read and will not be set again until the BERT has experienced another change of state. The setting of this status bit can cause a hardware ...
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FTCLK. The HRCLK checks for the presence of the FTCLK. On reset, both the LOTC and LORC status bits will be set and then immediately cleared if the clock is present. Bit 11: Loss Of ...
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Figure 4-5. HDLC Status Bit Flow Transmit Packet End Signal from HDLC Internal Transmit Low Water Mark Signal from HDLC Internal Receive High Water Mark Signal from HDLC Internal Receive Packet Start Signal from HDLC Internal Receive Packet End Signal ...
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Figure 4-6. T2E2SR1 Status Bit Flow Internal LOF Signal from Alarm Latch T2/E2 Framer 1 Change in State Detect Internal LOF Signal from Alarm Latch T2/E2 Framer 2 Change in State Detect Internal LOF Signal from Alarm Latch T2 Framer ...
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Figure 4-7. T2E2SR2 Status Bit Flow Internal RAI Signal from Alarm Latch T2/E2 Framer 1 Change in State Detect Internal RAI Signal from Alarm Latch T2/E2 Framer 2 Change in State Detect Internal RAI Signal from Alarm Latch T2 Framer ...
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Figure 4-9. T3E3SR Status Bit Flow Receive LOS Alarm Latch Signal from T3/E3 Framer Change in State Detect Receive LOF Alarm Latch Signal from T3/E3 Framer Change in State Detect Receive AIS Alarm Latch Signal from T3/E3 Framer Change in ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — T2E2SR2 Default — 0 Bit # 15 14 Name — — Default — — Bit 0: One-Second Timer Boundary Occurrence (OST interrupt masked 1 = interrupt ...
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Test Register Description Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default — — Bit # 15 14 Name — — Default — — Bits Factory Test Bits (FT0 to FT5). ...
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T3/E3 FRAMER On the receive side, the T3/E3 framer locates the frame boundaries of the incoming data stream and monitors the data stream for alarms and errors. Alarms are detected and reported in T3/E3 Status Register ...
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T3/E3 Framer Control Register Description Register Name: Register Description: Register Address: Bit # 7 6 Name DLB LLB Default 0 0 Bit # 15 14 Name — PLB Default — 0 Bit 0: T3/E3 Transmit Alarm Indication Signal (TAIS). ...
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Bit 7: T3/E3 Diagnostic Loopback Enable (DLB). See loopback disable loopback 1 = enable loopback Bit 8: E3 Code Violation Enable (E3CVE). This bit is ignored in the T3 mode. This bit is used in the E3 mode ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MEIMS FBEIC1 Default 0 0 Bit # 15 14 Name — — Default — — Bit 0: BiPolar Violation Insert (BPVI). A zero to one transition on this bit ...
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Bits 5 and 6: Frame Bit Error Insert Control Bits 0 and 1 (FBEIC0 and FBEIC1). FBEIC1 FBEIC0 T3 Mode: A single F-bit error Mode: A single FAS word of 1111000000 is generated instead of the normal ...
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T3/E3 Framer Status and Interrupt Register Description Register Name: Register Description: Register Address: Bit # 7 6 Name — RSOF Default — — Bit # 15 14 Name — — Default — — Note: See Figure 5-1 for details ...
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Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. Bit 6: Receive T3/E3 Start Of Frame (RSOF). This latched read-only event status ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — RSOF Default — 0 Bit # 15 14 Name — — Default — — Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: ...
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Table 5-1. T3 Alarm Criteria ALARM/ DEFINITION CONDITION AIS Alarm Indication Signal Properly framed 1010... pattern, which is aligned with the 1 just after each overhead bit and all C bits are set to zero LOS Loss Of Signal (Note ...
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Table 5-2. E3 Alarm Criteria ALARM/ DEFINITION CONDITION AIS Alarm Indication Signal Unframed all ones LOS Loss Of Signal (See note) LOF Loss Of Frame Too many FAS errors RAI Remote Alarm Indication Inactive: Bit 11 of the frame = ...
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Bit 5: Severely Errored Framing Event Detected (SEFE). This latched read-only event-status bit will be set to a one each time the DS3112 has detected either three or more F bits in error out of 16 consecutive F bits (T3 ...
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T3/E3 Performance Error Counters There are six error counters in the DS3112. All of the errors counters are 16 bits in length. The host has three options as to how these errors counters are updated. The device can be ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name FE7 FE6 Default — — Bit # 15 14 Name FE15 FE14 Default — — Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name CPE7 CPE6 Default — — Bit # 15 14 Name CPE15 CPE14 Default — — Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 ...
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M13/E13/G.747 MULTIPLEXER AND T2/E2/G.747 FRAME Note that if the DS3112 is used as a stand-alone T3/E3 framer and the multiplexer functionality is disabled, then the registers and functionality described in this section are not applicable and should be ignored ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — LOFG7 Default — 0 Bit # 15 14 Name — — Default — — Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 ...
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T2/E2/G.747 Framer Status and Interrupt Register Description Register Name: Register Description: Register Address: Bit # 7 6 Name IELOF LOF7 Default 0 - Bit # 15 14 Name IEAIS AIS7 Default 0 - Note: See Figure 6-1 for details ...
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Figure 6-1. T2E2SR1 Status Bit Flow Internal LOF Signal from Alarm Latch T2/E2 Framer 1 Change in State Detect Internal LOF Signal from Alarm Latch T2/E2 Framer 2 Change in State Detect Internal LOF Signal from Alarm Latch T2 Framer ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name IERAI RAI7 Default 0 — Bit # 15 14 Name E2SOF4 E2SOF3 Default — — Note: See Figure 6-2 for details on the signal flow for the status bits ...
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Table 6-1. T2 Alarm Criteria ALARM/ DEFINITION CONDITION Alarm Indication Signal AIS Unframed all ones Loss Of Frame LOF Too many F bits or M bits in error Remote Alarm Indication RAI Inactive Active ...
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T1/E1 AIS Generation Control Register Description Via the T1/E1 Alarm Indication Signal (AIS) Control Registers, the host can configure the DS3112 to generate an unframed all ones signal in either the transmit or receive paths on the 28 T1 ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name AIS8 AIS7 Default 0 0 Bit # 15 14 Name AIS16 AIS15 Default 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 ...
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T1/E1 LOOPBACK AND DROP AND INSERT FUNCTIONALITY On the T1 and E1 ports, the DS3112 has loopback capability in both directions. There is a per-port line loopback that loops the receive side back to the transmit side and a ...
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T1/E1 Loopback Control Register Description Register Name: Register Description: Register Address: Bit # 7 6 Name LLB8 LLB7 Default 0 0 Bit # 15 14 Name LLB16 LLB15 Default 0 0 Note: Bits that are underlined are read-only; all ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name DLB8 DLB7 Default 0 0 Bit # 15 14 Name DLB16 DLB15 Default 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name LB8 LB7 Default 0 0 Bit # 15 14 Name LB16 LB15 Default 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name LB24 LB23 Default 0 0 Bit # 15 14 Name — — Default — — Note: Bits that are underlined are read-only; all other bits are read-write. Bits 17 ...
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T1 Line Loopback Command Status Register Description Register Name: Register Description: Register Address: Bit # 7 6 Name LLB8 LLB7 Default — — Bit # 15 14 Name LLB16 LLB15 Default — — Note: See Figure 7-1 for details ...
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Figure 7-1. T1LBSR1 and T1LBSR2 Status Bit Flow Internal T1 Loopback Command Signal from T2/E2 Framer Internal T1 Loopback Command Signal from T2/E2 Framer Internal T1 Loopback Command Signal from T2/E2 Framer 7.7 T1/E1 Drop and Insert Control Register Description ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default — — Bit # 15 14 Name — — Default — — Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 ...
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BERT The BERT block can generate and detect the following patterns: • Pseudorandom patterns 2 • A repetitive pattern from bits in length • Alternating (16-bit) words that flip every 1 to 256 words The BERT ...
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Bits 8 to 12: Transmit BERT Port Select Bits (TBPS0 to TBPS4). These bits determine if the transmit BERT will be used to replace the normal transmit data on any of the 16/21 E1 ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name PBS TINV Default 0 0 Bit # 15 14 Name IESYNC IEBED Default 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: ...
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Bits 8 to 11: Repetitive Pattern Length Bits 5 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is the MSB of a nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name EIB2 EIB1 Default — 0 Bit # 15 14 Name AWC7 AWC6 Default 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RP7 RP6 Default 0 0 Bit # 15 14 Name RP15 RP14 Default 0 0 Register Name: Register Description: Register Address: Bit # 7 6 Name RP23 RP22 Default ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name BBC7 BBC6 Default 0 0 Bit # 15 14 Name BBC15 BBC14 Default 0 0 Register Name: Register Description: Register Address: Bit # 7 6 Name BBC23 BBC22 Default ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — RA1 Default — — Bit # 15 14 Name BEC7 BEC6 Default 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: ...
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Figure 8-1. BERT Status Bit Flow Internal RLOS Signal from Alarm Latch BERT Change in State Detect Internal Bit Event Latch Error Detected Signal from BERT Internal Counter Overflow Event Latch Signal from BERT NOTE: ALL EVENT AND ALARM LATCHES ...
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HDLC CONTROLLER The DS3112 contains an on-board HDLC controller with 256-byte buffers in both the transmit and receive paths. When the device is operated in the T3 mode, the HDLC controller is only active in the C- Bit Parity ...
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HDLC controller will send an abort of seven ones in a row (FEh) followed by a continuous transmission of either 7Eh (flags) or FFh (idle) and the Transmit FIFO Underrun (TUDR) status bit will be set. When ...
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Bit 5: Transmit HDLC Reset (THR). A zero to one transition will reset the Transmit HDLC controller. Must be cleared and set again for a subsequent reset. A reset will flush the current contents of the transmit FIFO and cause ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name D7 D6 Default — — Bit # 15 14 Name — — Default — — Note 1: When the CPU bus is operated in the 8-bit mode (CMS = ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name D7 D6 Default 0 0 Bit # 15 14 Name — — Default — — Note 1: When the CPU bus is operated in the 8-bit mode (CMS = ...
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Bit 4: Receive FIFO High Watermark (RHWM). This read-only real-time status bit will be set to a one when the receive FIFO contains more than the number of bytes configured by the Receive High Watermark Setting control bits (RHWMS0 to ...
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FIFO has been read from and then allowed to fill up again). The setting of this bit can cause a hardware interrupt to occur if the ROVR bit in the Interrupt Mask for HSR (IHSR) register is set ...
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Figure 9-1. HSR Status Bit Flow Transmit Event Latch Packet End Signal from HDLC Internal Transmit Low Water Mark Signal from HDLC Internal Receive High Water Mark Signal from HDLC Internal Receive Packet Start Event Latch Signal from HDLC Internal ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TUDR RPE Default 0 0 Bit # 15 14 Name RABT — Default 0 — Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: ...
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FEAC CONTROLLER The DS3112 contains an onboard FEAC controller. When the device is operated in the T3 mode, the FEAC controller is only active in the C-Bit Parity Mode. When the device is operated in the E3 mode, the ...
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Bits 6 and 7: Transmit FEAC Codeword Select Bits 0 and 1 (TFS0 and TFS1). These two bits control what two available codewords should be generated. Both TFS0 and TFS1 are edge triggered. To change the action, the host must ...
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FEAC Status Register Description Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default — — Bit # 15 14 Name RFFO RFFE Default — — Note: Bits that are underlined are read-only; all other ...
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JTAG The DS3112 device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, IDCODE DS3112 contains the following items that meet the requirements set by the IEEE 1149.1 Standard Test Access Port ...
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TAP Controller State Machine Description This section describes the operation of the test access port (TAP) controller state machine ( The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising ...
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Test-Logic-Reset Upon power-up of the DS3112, the TAP controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic on the DS3112 will operate normally. 11.1.2 Run-Test-Idle Run-Test-Idle is used between scan ...
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Capture-IR The Capture-IR state is used to load the shift register in the Instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, ...
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Instruction Register and Instructions The Instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected ...
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CLAMP All digital outputs will output data from the boundary scan parallel output while connecting the Bypass Register between JTDI and JTDO. The outputs will not change during the CLAMP instruction. 11.3 Test Registers IEEE 1149.1 requires a minimum ...
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BIT SYMBOL PIN 22 FTD B10 23 FTCLK A10 FTSOF_ENB_ 24 Control bit N 25 FTSOF_OUT A11 26 FTSOF_IN A11 27 FTMEI C11 28 HRNEG C12 29 HRCLK A13 30 HRPOS B13 31 HTNEG A14 32 HTCLK B14 33 HTPOS ...
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BIT SYMBOL PIN 70 LRCLK20 V19 71 LRDAT20 W20 72 LTCLK19 Y20 73 LTDAT19 W19 74 LRCLK19 V18 75 LRDAT19 Y19 76 LTCLK18 W18 77 LTDAT18 V17 78 LRCLK18 U16 79 LRDAT18 Y18 80 LTCLK17 W17 81 LTDAT17 V16 82 ...
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BIT SYMBOL PIN 119 LRDAT8 W5 120 LTCLK7 V5 121 LTDAT7 Y4 122 LRCLK7 Y3 123 LRDAT7 U5 124 LTCLK6 V4 125 LTDAT6 W4 126 LRCLK6 Y2 127 LRDAT6 W3 128 LTCLK5 V3 129 LTDAT5 W1 130 LRCLK5 V2 131 ...
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BIT SYMBOL PIN 168 CD13_OUT G3 169 CD13_IN G3 170 CD12_OUT F1 171 CD12_IN F1 172 CD11_OUT F2 173 CD11_IN F2 174 CD10_OUT G4 175 CD10_IN G4 176 CD9_OUT F3 177 CD9_IN F3 178 CD8_OUT E1 179 CD8_IN E1 180 ...
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DC ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin with Respect to V Supply Voltage (V ) Range with Respect Operating Temperature Range………………………………………………………………..0°C to +70°C Storage Temperature Range………………………………………………………………-55°C to +125°C Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 ...
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AC ELECTRICAL CHARACTERISTICS Table 1 -1. AC Characteristics—Low-Speed (T1 and E1) Ports 3 = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13- 1.) PARAMETER LRCLK/LRCCLK/LTCLK/LTCCLK Clock Period LRCLK Clock High Time ...
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Figure 13-1. Low-Speed (T1 and E1) Port AC Timing Diagram LRCLK (or LRCCLK) / LTCLK (or LTCCLK) Normal Mode LRCLK (or LRCCLK) / LTCLK (or LTCCLK) Inverted Mode LTDAT LRDAT 111 of 133 t3 ls_ac ...
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Table 13-2. AC Characteristics—High-Speed (T3 and E3) Ports = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13- 2.) PARAMETER HRCLK/HTCLK Clock Period HRCLK Clock Low Time HRCLK Clock High Time HRPOS/HRNEG Setup ...
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Table 13-3. AC Characteristics–Framer (T3 and E3) Ports = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13- 3.) PARAMETER FRCLK/FTCLK Clock Period FTCLK Clock Low Time FTCLK Clock High Time FTD/FTSOF Setup ...
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Table 13-4. AC Characteristics—CPU Bus (Multiplexed and Nonmultiplexed) = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13- 4, Figure 13-5, and Figure 13-11.) PARAMETER Setup Time for CA[7:0] Valid to CCS Active ...
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Figure 13-4. Intel Read Cycle (Nonmultiplexed) CA[7:0] CD[15:0] CWR CCS CRD Figure 13-5. Intel Write Cycle (Nonmultiplexed) CA[7:0] CD[15:0] CRD CCS CWR Address Valid Data Valid Address Valid 115 of 133 ...
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Figure 13-6. Motorola Read Cycle (Nonmultiplexed) CA[7:0] CD[15:0] CR/W t1 CCS CDS Figure 13-7. Motorola Write Cycle (Nonmultiplexed) CA[7:0] CD[15:0] CR/W CCS CDS Address Valid Data Valid t2 t3 Address Valid 116 of 133 DS3112 t9 t5 ...
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Figure 13-8. Intel Read Cycle (Multiplexed) t13 CALE t11 Address CA[7:0] Valid t14 CD[15:0] t14 CWR CCS CRD NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST. Figure 13-9. ...
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Figure 13-10. Motorola Read Cycle (Multiplexed) t13 CALE t11 Address CA[7:0] Valid t14 CD[15:0] t14 CR/W CCS CDS NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST. Figure 13-11. ...
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Table 1 -5. AC Characteristics—JTAG Test Port Interface 3 = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13-1 2.) PARAMETER JTCLK Clock Period JTCLK Clock Low Time JTCLK Clock High Time JTMS/JTDI ...
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Table 13-6. AC Characteristics—Reset and Manual Error Counter/Insert Signals = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13 PARAMETER RST Low Time FRMECU/FTMEI High Time FRMECU/FTMEI Low Time Figure 13-13. ...
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APPLICATIONS AND STANDARDS OVERVIEW 14.1 Application Examples Figure 14-1 and Figure 14-2 example of a channelized T3/E3 application. It shows the DS3112 being used to multiplex and demultiplex a T3/E3 data stream into either 28 T1 data streams or ...
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Figure 14-2. Unchannelized Dual T3/E3 Application DS3134 PCI CHATEAU Bus 256 Channel HDLC Controller 14.2 M13 Basics M13 multiplexing is a two-step process of merging 28 T1 lines into a single T3 line. First, four of the T1 lines are ...
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T2 Framing Structure To understand the M12 function users must understand T2 framing. The T2 frame structure is made up of four subframes called M subframes ( another (...M1/M2/M3/M4/M1/M2...) to make up the complete T2 M frame data structure. ...
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Figure 14-3. T2 M-Frame Structure M1 Subframe Info C1 Info (0) Bits Bits M2 Subframe Info C1 Info (1) Bits Bits M3 Subframe Info C1 Info (1) Bits Bits M4 Subframe ...
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T3 Framing Structure As with M12, to understand the M23 function requires an understanding of T3 framing. The T3 frame structure is very similar to the T2 frame structure; however made up of seven M subframes (see ...
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C-Bit Parity Mode Unlike the M23 application that uses the C bits for stuffing, the C-Bit Parity mode assumes that a stuff bit should be placed at every opportunity and, hence, the C bits can be used for other ...
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Figure 14-5. T3 M-Frame Structure M1 Subframe Info F1 Info C1 Bits (1) Bits M2 Subframe Info F1 Info C1 Bits (1) Bits M3 Subframe Info F1 Info C1 Bits (1) ...
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Figure 14-6. T3 Stuff Block Structure M1 F4 Stuff Info Subframe Bit 1 Bit Info Stuff Subframe Bit 1 Bit Info Info Subframe Bit 1 Bit Info Info Subframe Bit 1 ...
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E2 Framing Structure and E12 Multiplexing The E2 frame structure is made up of four 212-bit sets ( after another (...Set1/Set2/Set3/Set4/Set1...) to make up the complete E2 frame structure. The Frame Alignment Signal (FAS) is placed in the first ...
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Figure 14-7. E2 Frame Structure Set 1 Bit 1 FAS (1111010000) RAI Sn Set 2 Bit Set 3 Bit Set 4 Bit ...
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G.747 Basics G.747 multiplexing is a mixture of T3 and E1 two-step process of merging 21 E1 lines into a single T3 line. First, three of the E1 lines are merged into a single T2 rate ...
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G.747 Framing Structure and E12 Multiplexing The G.747 frame structure is made up of five 168-bit sets after another (...Set1/Set2/Set3/Set4/Set5/Set1...) to make up the complete G.747 frame structure. The Frame Alignment Signal (FAS) is placed in the first 9 ...
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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. 133 of 133 © 2006 Maxim Integrated Products ...