DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 50

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 7: T3/E3 Diagnostic Loopback Enable (DLB). See
loopback.
Bit 8: E3 Code Violation Enable (E3CVE). This bit is ignored in the T3 mode. This bit is used in the E3 mode to
configure the BiPolar Violation Count Register (BPVCR) to count either BiPolar Violations (BPV) or Code
Violations (CV). A BPV is defined as consecutive pulses (or marks) of the same polarity that are not part of a
HDB3 codeword. A CV is defined in ITU O.161 as consecutive BPVs of the same polarity.
Bits 9 and 10: T3/E3 Frame Error Counting Control Bits 0 and 1 (FECC0 and FECC1).
Bit 11: Error Counting Control (ECC). This bit is used to control whether the device will increment the error
counters during Loss Of Frame (LOF) conditions. It only affects the error counters that count errors that are based
on framed information and these include the following:
When this bit is set low, these error counters will not be allowed to increment during LOF conditions. When this bit
is set high, these error counters will be allowed to increment during LOF conditions.
Bit 12: Automatic FEBE Defeat (AFEBED). This bit is ignored in the E3 mode and in the T3 mode when the
device is not configured in the C-Bit Parity Mode. When this bit is low, the device will automatically insert the
FEBE codes into the transmitted data stream by setting all three C bits in Subframe 4 to zero.
Bit 13: Transmit FEBE Setting (TFEBE). This bit is only active when AFEBED is active (i.e., AFEBED = 1).
When this bit is low, the device will force the FEBE code to 111 continuously. When this bit is set high, the device
will force the FEBE code to 000 continuously.
Bit 14: T3/E3 Payload Loopback Enable (PLB). See
loopback.
FECC1
0
0
1
1
0 = disable loopback
1 = enable loopback
0 = count BPV
1 = count CV
Frame Error Counter (when it is configured to count frame errors, not LOF occurrences)
T3 Parity Bit Error Counter
T3 C-Bit Parity Error Counter
T3 Far End Block Error or E3 RAI Counter
0 = stop the FECR/PCR/CPCR/FEBECR error counters from incrementing during LOF
1 = allow the FECR/PCR/CPCR/FEBECR error counters to increment during LOF
0 = automatically insert FEBE codes in the transmit data stream based on detected errors
1 = use the TFEBE control to determine the state of the FEBE codes
0 = force FEBE to 111 (null state)
1 = force FEBE to 000 (active state)
0 = disable loopback
1 = enable loopback
FECC0
0
1
0
1
FRAME ERROR COUNT REGISTER (FECR) CONFIGURATION
T3 Mode: Count Loss Of Frame (LOF) Occurrences
E3 Mode: Count Loss Of Frame (LOF) Occurrences
T3 Mode: Count Both F Bit and M Bit Errors
E3 Mode: Count Bit Errors in the FAS Word
T3 Mode: Count Only F Bit Errors
E3 Mode: Count Word Errors in the FAS Word
T3 Mode: Count Only M Bit Errors
E3 Mode: Illegal State
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Figure 1-1
Figure 1-1
and
and
Figure 1-2
Figure 1-2
for a visual description of this
for a visual description of this
DS3112